Manuel Arcieri, Paolo Zuliani, Giovanni Carotenuto, Meryam Carrus, Tiziana Castrignanò
Quantum computing offers great potential for solving intractable computational challenges in bioinformatics, yet the existing literature remains dominated by speculative proposals rather than empirical evidence. To separate theoretical promise from practical reality, this review systematically assesses the empirical state of quantum computing applications across biological domains. We analyzed fifty-three experimental studies spanning sequence analysis, structural biology, phylogenetics, and biomedical machine learning, evaluating them based on their underlying computational paradigms, dataset scales, comparisons against classical baselines, and adherence to open-science reproducibility standards. Our investigation reveals that, while all comparative studies report performance that matches or exceeds that of classical methods, the vast majority rely on simulated environments or quantum-inspired classical heuristics rather than on physical quantum hardware. Moreover, nearly 77% of the evaluated implementations are restricted to heavily reduced toy datasets due to current technological constraints. Severe reproducibility issues plague the field, with just 30% of the studies providing both publicly accessible source code and experimental data. Although quantum bioinformatics has successfully produced viable proof-of-concept prototypes, the field is fundamentally limited by hardware scaling bottlenecks and a lack of standardized benchmarking. To move from conceptual demonstrations to practical scientific impact, we recommend that the community should prioritize rigorous reproducibility practices, establish transparent evaluation metrics, and clearly distinguish genuine quantum execution from classical simulation.
Current technologies allow for the sequencing of microbial communities directly from the environment without prior culturing. One of the major problems when analyzing a microbial sample is to taxonomically annotate its reads to identify the species it contains. In this study, we delve into an evaluation of how variations in the reference database impact classification performance. This aspect assumes paramount significance, particularly when considering the continuous evolution and expansion of the NCBI Reference Sequence database (RefSeq) over time. The aim of this study is to analyze the influence of RefSeq database size and composition on taxonomic identification performance using Kraken 2, a widely used taxonomic classification and profiling method. We found that resource-efficient Kraken 2 Lite (capped) databases, which can be run on standard laptops, generally exhibit lower classification accuracy compared to full reference databases that require high-performance computing infrastructure. The size of the RefSeq database and its growth affect the performance of the k-mer-based algorithms in addition to the computing resources need. We reported that changes in RefSeq reference database over time influenced the accuracy of metagenomic taxonomic classification, and training the classifier with more data, for example, new species, worsen the results especially on the most complex microbial communities.
Binary Neural Networks (BNNs) perform competitively in practical image classification tasks. In particular, their accuracy is similar to that obtained by full-precision models tailored to edge devices. BNNs are amenable for devices with constrained resources, since they employ just one bit to store inputs and weights; hence, their storage requirements are low. Moreover, BNN computations utilize XNOR operations, which are implemented efficiently using simple hardware structures. However, supporting BNNs efficiently on edge devices is challenging since they perform many memory accesses to load weights, hindering their benefits. In BNNs, weights and inputs are stored using one bit, and several of them are packed together as a sequence of bits. In this work, the number of unique sequences representing a set of weights is observed to be low. In addition, a small group of unique sequences is seen to be used more frequently than others. Accordingly, this observation is exploited by using variable length encoding to represent the most commonly used sequences and decompressing them during inference. Commonly, BNNs employ floating-point values to store the weights for the output layer, aiming to obtain competitive accuracy. This further magnifies the storage requirements and significantly affects performance. In this work, it is observed that using traditional quantization schemes to quantize these weights negatively affects network accuracy. Then, it is shown that one can use a small number of bits to store most of the values in the output layer without negatively impacting accuracy by carefully quantizing the weights that fall outside a given range. Finally, an efficient quantization scheme for the output layer is proposed. A previously proposed FPGA accelerator is extended with the required hardware to implement the proposed schemes. The proposal is evaluated on a Pynq Z1 device. Our techniques reduce memory requirement by 1.5 × and improve performance by 2.2 × on average.
The memory wall phenomenon—where advances in processor performance significantly outpace those in memory subsystems-poses a fundamental challenge for contemporary computing systems. In memory-bound applications, memory subsystem behavior dominates performance, yet existing analysis approaches present significant limitations: detailed microarchitectural simulators require days to weeks to simulate modest workloads; hardware performance counters provide only aggregate statistics that obscure temporal and spatial access patterns; and scaled simulation approaches face challenges in capturing contention effects, bandwidth saturation, and interference patterns that emerge at larger scales. These limitations reflect a processor-centric design philosophy—in both performance analysis tools and system co-design methodologies—that is increasingly misaligned with memorybound workloads, where a detailed understanding of memory access patterns, cache hierarchy interactions, and contention is critical for effective optimization. This paper presents an integrated framework for memory-centric analysis that enables effective hardware-software co-design. We describe practical trace collection techniques, including hardware assisted processor tracing with minimal overhead and portable software-based instrumentation with statistical sampling. We present multi-perspective analysis methods that examine memory behavior from temporal, sequential, spatial, and relational viewpoints, revealing distinct optimization opportunities invisible in aggregate metrics. For example, a data structure switch from an open to a closed hash table in the miniVite graph application—guided by spatial anticipation metrics—improved hardware prefetcher utilization and delivered a 1.8 × runtime improvement, a benefit invisible to aggregate performance counters. We detail an architectural modeling framework that uses sampled traces with temporal interpolation and confidence-based filtering to evaluate cache and memory configurations. Evaluation on representative benchmarks demonstrates that this framework achieves practical accuracy (L2 cache errors of 2.64%, confidence-filtered L3 errors of 9.92%, bandwidth errors of 7.33%) while providing substantial speedup (26.8 ×) over cycle-accurate simulation, enabling rapid design space exploration. We demonstrate how this integrated framework enables systematic identification of both hardware optimizations (memory controller tuning, bank partitioning, NUMA configuration) and software optimizations (data layout restructuring, pre-fetching strategies, and memory-aware scheduling). Through this comprehensive treatment of the memory-centric analysis pipeline—from trace collection through architectural modeling to co-design application—we provide researchers and practitioners with practical techniques for addressing memory bottlenecks in contemporary computing systems.
Mills Staylor, Arup Kumar Sarker, Gregor von Laszewski, Geoffrey C. Fox, Yue Cheng, Judy Fox
Data is found everywhere, from health and human infrastructure to the surge of sensors and the proliferation of internet-connected devices. To meet this challenge, the data engineering field has expanded significantly in recent years in both research and industry. Traditionally, data engineering, Machine Learning, and AI workloads have been run on large clusters within data center environments, requiring substantial investment in hardware and maintenance. With the rise of the public cloud, it is now possible to run large applications across nodes without owning or maintaining hardware. Serverless functions such as AWS Lambda provide horizontal scaling and precise billing without the hassle of managing traditional cloud infrastructure. However, when processing large datasets, users often rely on external storage options that are significantly slower than direct communication typical of HPC clusters. We introduce Cylon, a high-performance distributed data frame solution that has shown promising results for data processing using Python. We describe how we took inspiration from the FMI library and designed a serverless communicator to tackle communication and performance issues associated with serverless functions. With our design, we demonstrate that the scaling efficiency of AWS Lambda achieves within 6.5% of serverful AWS (EC2) at 64 nodes, based on implementing direct communication via NAT Traversal TCP Hole Punching.
