Advances in Hardware Accelerators for Artificial Intelligence

Artificial intelligence (AI) workloads, spanning deep learning training, real-time inference, graph neural networks, and generative models, continue to escalate in complexity, scale, and computational intensity. Driven by models with trillions of parameters and the shift toward edge deployment, hardware accelerators have emerged as critical enablers, surpassing the limitations of general-purpose CPUs and GPUs. Modern AI systems innovate at multiple levels—exploiting spatial parallelism, domain-specific compute engines, novel memory hierarchies, and advanced interconnects to deliver unprecedented performance per watt. Leading high-tech companies have pioneered accelerators like Google's TPUs, NVIDIA's GPUs with tensor cores, Apple's Neural Engine, and Huawei's Ascend chips, integrating systolic arrays, sparsity exploitation, and mixed-precision arithmetic for efficiency. Alongside accelerators developed by established industry giants, the field is also being shaped by innovative hardware platforms from emerging players such as Cerebras, SambaNova, and others, which explore wafer-scale computing, reconfigurable dataflow execution, and other unconventional architectural approaches for AI.These architectures address the von Neumann bottleneck through paradigms like dataflow processing, where computations activate dynamically with data availability, minimizing control overheads and enabling massive fine-grained parallelism. In-memory computing (PIM/CIM), neuromorphic designs mimicking synaptic plasticity, and photonic/optical accelerators further push boundaries, reducing data movement costs that dominate AI energy budgets. As AI integrates with high-performance computing (HPC), edge devices, and emerging quantum hybrids, hardware must scale to exascale-like clusters while maintaining programmability and resilience.However, this evolution introduces profound challenges. Efficient multi-level parallelism (from chips to racks), scalable memory systems tackling bandwidth/latency walls, heterogeneous integration of AI engines, and mitigation of faults in dense silicon are pivotal. In shared cloud/edge environments, resource isolation, security, and predictability become essential, alongside handling silent data corruptions (SDCs) and software faults in AI pipelines. Hardware-software co-design, programmable fabrics, and modelling trade-offs in sparsity, quantization, and sustainability are crucial for navigating this landscape.This Research Topic aims to highlight novel hardware and system-level advancements in AI accelerators, emphasizing special architectures to drive efficient, scalable intelligence for scientific discovery, industry applications, and beyond.We welcome original research articles, reviews, perspectives, and case studies on advances in hardware accelerators for AI. Topics of interest include, but are not limited to:- Dataflow architectures, systolic arrays, and spatial accelerators for DNNs/GNNs/sparse workloads- Industry AI accelerators (TPUs, NPUs, GPUs) and optimizations for training/inference- In/near-memory computing, neuromorphic chips, photonic/quantum hybrids- Energy-efficient edge AI hardware, fault tolerance, and HPC-scale integration- Memory hierarchies, interconnects, and multi-level parallelism for AI systems- Hardware-software co-design, benchmarking, and workload analysis- Resource partitioning, isolation, and programmability in heterogeneous environments- Exploitation of chiplets, 3D integration, and emerging silicon for AISubmissions integrating theoretical innovation with empirical evaluations, real-world deployments, or domain-specific case studies (e.g., sustainability metrics, open datasets/code) are particularly encouraged. Topic editors: Nenad Korolija, Veljko Milutinovic Source: https://www.frontiersin.org/research-topics/77447/advances-in-hardware-accelerators-for-artificial-intelligence