Challenges and research opportunities in silicon-based subwavelength grating technologies

1 Introduction

Silicon photonics has revolutionized the field of optical technology by enabling the integration of photonics with mature complementary metal-oxide-semiconductor (CMOS) fabrication processes. Among the many innovations within this platform, SWGs have emerged as a versatile and powerful building block, enabling unprecedented control over light propagation, confinement, dispersion, and polarization in silicon-based photonic devices. However, despite their tremendous potential, there are many roadblocks preventing the full deployment and commercialization of this technology. While significant advances have been made in the design and demonstration of silicon photonics devices, a persistent gap remains between theoretical predictions and experimental validation. Variations in fabrication processes, material properties, and device performance often make it difficult to establish standardized design methodologies and performance benchmarks across different platforms. These challenges are further amplified in SWG-based devices, where optical performance is highly sensitive to structural and dimensional variations and fabrication imperfections. As a result, device scalability, performance reproducibility, and manufacturability remain key barriers to the widespread adoption and commercialization of SWG technology. Overcoming these barriers will require the development of comprehensive design frameworks, standardized benchmarking protocols, and manufacturing-aware design methodologies that can facilitate technology transfer from research laboratories to commercial production. This paper reviews the key challenges limiting the practical implementation of SWG-based photonic devices and highlights recent strategies and emerging approaches aimed at addressing these challenges to enable the next-generation of scalable and manufacturable silicon photonic systems.

Previous reviews have provided comprehensive discussions of SWG operating principles, effective-medium theory, device architectures, and applications. However, comparatively less attention has been given to the challenges that arise when these structures move beyond individually optimized laboratory demonstrations toward repeatable foundry fabrication and product-level deployment. These challenges include the effects of process variability, differences between simulated and fabricated geometries, inconsistent performance reporting, limited availability of validated compact models and SWG-specific process design kit components, and the cost and complexity of wafer-level testing and packaging. The unique contribution of this review is therefore its focus on the complete translation pathway from SWG physics and device demonstration to standardized validation, scalable manufacturing, and commercialization. We connect the geometrical and physical sensitivities of SWG structures with practical requirements for design-for-manufacturability, process monitoring, benchmarking, foundry qualification, electronic–photonic design automation, testing, and packaging. Based on this synthesis, we propose a minimum reporting set for SWG devices and present roadmaps identifying the technical capabilities and collaborative efforts needed to support reproducible design and deployment. Rather than reviewing every reported SWG device architecture, the article emphasizes representative studies that reveal broader challenges and emerging solutions related to fabrication tolerance, experimental validation, and manufacturing readiness.

The remainder of this article is organized as follows. Section 2 summarizes the physical principles of SWG waveguides and the geometrical parameters governing their performance and fabrication sensitivity. Section 3 examines approaches to bridging the gap between theory and experimental validation. Section 4 discusses efforts to create standards and benchmarks to guide SWG design. Section 5 discusses scalability and manufacturability of SWG devices. Section 6 considers interdisciplinary applications and commercialization, ecosystem development, and commercialization pathways. Finally, Section 7 summarizes the principal findings and identifies priorities for the future deployment of SWG technologies.

2 Physics of SWG

SWGs are photonic structures composed of periodically spaced silicon slabs of segment length a and period Λ. An SWG waveguide can support the propagation of the fundamental Bloch-mode if the period is lower than the first Bragg threshold, given by Equation 1 where λ 0 is the operating wavelength and n eff is the effective index of the waveguide. In the deep-subwavelength regime ( Λ ≪ λ 0 ), the waveguide can be described by the effective medium approximation (EMA) and can be approximated to a waveguide with a solid core as shown in Figure 1 (Luque-González et al., 2021). In this case, the waveguide is modeled as a uniaxial anisotropic material with refractive index components ( n ‖ ) and ( n ⊥ ), given byandwhere η = a / Λ represents the duty cycle of the grating, and the subscripts ‖ and ⊥ denote directions parallel and perpendicular to the grating interfaces, respectively. These first-order effective-medium expressions are applicable in the deep-subwavelength regime. As the period approaches the first Bragg threshold, the effects of spatial dispersion, local field confinement, and band-edge phenomena must be taken into account, and hence a more rigorous description through Bloch-Floquet theory. The waveguide in each unit cell is described by Equation 4 where u k ( x , y , z ) = u k ( x , y , z + Λ ) and k z is the Bloch propagation constant. In a practical device, approaching the Bragg regime can lead to band edge effects such as back-reflections and radiation loss due to stochastic or systematic fabrication imperfections which move the waveguide into the Bragg regime. This requires more rigorous simulations which are more time-consuming than a homogenized waveguide below the Bragg threshold.

Λ < λ 0 2 n eff (1)

n ‖ 2 = η n Si 2 + 1 − η n clad 2 (2)

1 n ⊥ 2 ≈ η 1 n Si 2 + 1 − η 1 n clad 2 (3)

E x , y , z = u k x , y , z e − i k z z (4)

The asymmetry of the waveguide indices, as described by EMA, induces strong form birefringence Δ n eff = n TE − n TM. According to equation (Equations 2, 3), raising η increases n ‖ relative to n ⊥ thus increasing TE/TM splitting. Fabrication non-idealities, such as corner rounding and sidewall tilt, and finite Λ also affect anisotropy. Other fabrication non-idealities that can affect mode-confinement in SWG waveguides include waveguide width W, period Λ, segment length a, etch depth H, and sidewall angle θ S W. A conventional wire waveguide and SWG waveguide is shown in Figure 2 with the aforementioned dimensions.

W determines lateral mode confinement and hence width bias in fabrication directly affects n eff. Λ and a control η, which directly affects n eff, n g, Δ n eff. Deviations in H affect both n eff and group dispersion d n eff / d λ. When sidewall angle θ S W ≠ 9 0 o, vertical inversion symmetry is broken leading to TE-TM coupling, polarization conversion, and changes in both effective and group indices.

3 Bridging theory and experimental validation

Experimental validation remains a major challenge for silicon photonics in general. This is primarily due to differences in realized feature dimensions and dependent on the platform used, operation wavelength, period, duty cycle and device type. For applications at telecommunication wavelengths around 1550 nm, critical feature dimensions often fall within the ∼100 nm range (Ahmed, 2022; Sun et al., 2020). Researchers frequently rely on external foundries for device fabrication. The process variability depending on the foundry leads to longer design cycles, increased development costs, and additional barriers to rapid experimental validation. Furthermore, fabrication induced imperfections such as surface roughness, corner rounding, dimensional deviations, and, etch non-uniformities can complicate the application of EMA theory, which assumes ideal periodic structures and well-defined interfaces between materials of different refractive indices. Thus, devices must be designed by taking into account such imperfections. Figure 3 provides a roadmap towards design-for-manufacturability (DfM) for SWG-based devices. This framework will help in validation of simulated and fabricated prototypes which is currently lacking in literature.

It is important to distinguish minimum feature size from dimensional tolerance. While the feature sizes are reduced for SWG devices, the dimensional tolerances are not necessarily reduced. For instance, SWGs allow effective index engineering which can be used to deliberately reduce sensitivity to width variations and increase dimensional tolerance (Xiong et al., 2014). propose a polarization splitter and rotator (PSR) consisting of a silicon wire waveguide evanescently coupled to a SWG waveguide. By engineering the material index of the SWG waveguide, the fabrication tolerance of waveguide widths is enhanced ten-fold compared an analogous wire-waveguide PSR without SWGs.

Similarly (Fernández de Cabo et al., 2025), report a multimode, polarization-independent 3-dB power splitter based on a symmetric Y-junction assisted by two regions of SWG metamaterials. The device is designed on a 220 nm SOI platform with a minimum feature size of 100 nm and SWG period of 200 nm. Simulations and experiments demonstrate that the device maintains low excess loss across the full 700 nm bandwidth for dimensional deviations of Δ δ = ± 10 nm, and remains usable for Δ δ = ± 20 nm, with excess loss below 0.6 dB over 700 nm and below 0.3 dB over 500 nm. These results show that SWG metamaterials can enable relaxed fabrication tolerances without compromising broadband performance.

Another method to incorporate fabrication imperfections directly into the design process is through fabrication-aware inverse-design techniques, as demonstrated in (Raza et al., 2024). Similarly, lithographic and process tolerances can be accounted for through robust parametric and sensitivity analyses, where key design parameters are systematically varied within expected fabrication limits to evaluate device resilience and yield. An example of this approach was reported in (Huang and Huang, 2020).

The costs associated with the fabrication of SWG devices for experimental validation can be partially mitigated through the use of multi-project wafer (MPW) services, which aggregate designs from multiple research groups onto a single fabrication run and distribute fabrication costs among participants. MPW programs have played a critical role in accelerating the prototyping and validation of silicon photonic devices by providing researchers with affordable access to advanced fabrication technologies.

4 Standardization and benchmarking

There exists a significant lack of standardized performance metrics and benchmarking protocols in silicon photonics and this challenge is particularly pronounced for SWG technologies (Cheben et al., 2018; Luque-González et al., 2021). Unlike conventional silicon photonic components for which foundry process design kits (PDKs) provide validated device libraries, compact models, design workflows, SWG components often lack standardized design rules, fabrication guidelines, and consensus performance metrics (Hammood et al., 2025). Consequently, comparisons between devices reported by different research groups are frequently complicated by variations in measurement conditions, fabrication processes, and reporting methodologies.

Existing foundry PDKs include strip and rib waveguide libraries, with proprietary offering complemented by open-source platforms such as OpenEPDA and SiEPIC. However, support for SWG devices remains limited or absent in most commercial and open-source PDKs (Latkowski et al., 2019). Designers must perform custom electromagnetic simulations and device-specific optimization workflows for each device, increasing design complexity and development time. Figure 4 provides a framework for standardized reporting of designs for ease of foundry qualification.

A few groups such as Advanced Photonics Coalition (APC) (Advanced Photonics Coalition, 2025) and IEEE Standards Association (IEEE-SA) have initiated efforts to develop standards for silicon photonics due to growing interest in this domain. There is not much literature available specifically for SWG devices but the same standardization principles for standard silicon photonic components, including performance characterization, model validation, process qualification, and data reporting, can be applied to SWGs. Addressing these standardization gaps will be essential for improving device reproducibility, enabling foundry adoption, and accelerating the commercialization of SWG-enabled photonic systems. Table 1 lists some of the key challenges and the impact on deployment of this technology.

TABLE 1. Challenges in standardization and benchmarking of SWG devices.

To address the lack of standardization in silicon SWG devices, we here propose a set of minimum reporting set for SWG devices. This establishes a set of parameters that must be specified to enable direct benchmarking across fabrication platforms, improve reproducibility, and support development of SWG models in commercial PDKs.

• Unit cell geometry, layer stack, and material dispersion models: Complete unit cell geometry including grating period, segment length, width and height. Full stackup including substrate, buried oxide, core and cladding materials. Wavelength dependent dispersion n ( λ ) and k ( λ ) for all materials and assumed operating temperature.
• Experimentally measured critical dimensions: Experimentally measured critical dimensions (CDs) through SEM, AFM, or other methods. Characterization of fabrication non-idealities including segment length bias, sidewall angle, and corner rounding.
• Lithography and etching processes: Description of lithography tools, photo-resist system, etch chemistry, and cladding deposition method.
• Simulation method, boundary conditions, mesh, and convergence: Numerical simulation reports should specify the computational solver (e.g., 3D FDTD, RCWA, EME), spatial mesh discretization Δ x, Δ y and Δ z, boundary-condition setup, convergence test data.
• Optical performance and measurement uncertainty: insertion loss (dB), propagation loss (dB/cm), extinction ratio, and 1-dB/3-dB optical bandwidth, with 95% confidence intervals across multiple test dies.
• Wavelength range, polarization, temperature, and environment: polarization (TE/TM), spectral sweep range, stage temperature, and cladding environment (e.g., dry air, aqueous solution, gas).
• Coupling calibration and de-embedding procedures: normalization methodology (e.g., reference straight waveguides, TRL calibration). Number of calibration structures measured. Method used to extract coupler loss.
• Fabrication-tolerance analysis: Measured or simulated sensitivity to global CD bias and layer thickness. Impact of over- or under-etching and global dimensional bias on key figures of merit such as insertion loss, group index, and bandwidth.

5 Scalability and manufacturing challenges

The challenges facing scalable manufacturing of SWG structures are similar to that of conventional photonic integrated circuits (PICs) Achieving large-scale manufacturing of SWG-based photonic devices requires overcoming stringent uniformity tolerances, process variability, and lithographic limits that might exceed current foundry capabilities. Figure 5a by (Latkowski et al., 2019) shows a typical manufacturing chain for PICs while Figure 5b demonstrates the test process required for product development. In commercial silicon photonics processes, the 6σ spread of waveguide width and thickness variation can exceed 15 nm, introducing performance deviations that may be unacceptable for many SWG-based devices (Xing et al., 2022). Bridging the gap between design and fabrication therefore remains a critical challenge for the widespread deployment of SWG technologies. Recent efforts by companies such as Pre-fab Photonics have sought to address this issue using computer vision and deep learning models (PreFab Photonics, 2025). Keysight has recently released MetaOptic Designer which provides an automated workflow for the design, simulation, and optimization of metalenses and metasurface-based optical components. The tool significantly reduces the design complexity associated with metasurfaces by automating parameter sweeps, library generation, and layout synthesis Keysight Technologies (2025). At the industrial level, companies such as Broadcom, Intel, Cisco (Luxtera, Lightwire and Acacia) have led the development of high-volume silicon photonics manufacturing by enabling more than 10,000 integrated photonics components.

Luxtera has pioneered high-volume manufacturing for their optical transceivers using silicon photonics on both 200 mm and 300 mm substrates. Although many details of the manufacturing process remain proprietary, publicly available reports highlight the extensive investments required to achieve production-scale yields and reliability. These efforts included the development of their own PDKs by manufacturing intentionally shifted wafers to see the impact of process variations; comprehensive optical wafer acceptance test (O-WAT) were performed on every wafer to ensure no processing issues impacts device functionality; and optical sort (O-SORT) tests were developed for individual product dies to pass/fail based on performance specifications. In addition, Luxtera developed in-house laser source and fiber attach tools; while an industry-standard TEL Precio Prober was customized with a new optical probe-head designed by Luxtera for automated optoelectronic testing of devices on full cassettes of up to 25 wafers at once (Pinguet et al., 2018) to support large-scale manufacturing. The substantial infrastructure, expertise, and capital investment required for such manufacturing ecosystems highlight the significant barriers to entry faced by startups, small companies, and academic research laboratories.

5.1 Integration architecture: monolithic vs. hybrid

Monolithic integration, in which optical and electronic devices are co-fabricated on a single SOI substrate, offers low parasitic capacitance, reduced interconnect losses, improved energy efficiency, and higher integration density (Atabaki et al., 2018). However, monolithic integration requires simultaneous optimization of photonic and electronic fabrication processes which introduces considerable design and manufacturing complexity. Changes to the substrate, process flow, or technology platform can impact optical device performance. In SWG structures, periodic segmentation enhances the sensitivity of local phase to temperature and metal proximity. As a result, heaters and electrical interconnects must be placed at sufficient distance from the SWG core, and thermal simulations should be used to ensure that the effective index is not distorted by localized heating. These SWG-specific routing and heater constraints are more stringent than for uniform strip or rib waveguides, and should be reflected in foundry design rules.

Hybrid integration addresses many limitations by decoupling the fabrication of photonic and electronic circuits, enabling simpler, lower-cost photonics and independent use of cutting-edge CMOS technologies for electronic devices, and facilitating heterogeneous integration of multiple material platforms (Margalit et al., 2021). However, these advantages come at the cost of increased parasitic effects at electro-optic interfaces, packaging complexity, and stringent requirements for die-to-die alignment, micro-bump interconnects, and thermal management. Consequently, packaging and assembly often become dominant contributors to system cost and manufacturing complexity (Pinguet et al., 2018).

Back-end-of-line (BEOL) processing further modifies SWG effective index, dispersion, and optical confinement. As shown by (Wei et al., 2024), deep SiO 2 trenches etched down to the silicon core using a silicon nitride etch-stop layer can be integrated monolithically with insertion loss below 0.09 dB per trench, provided the trench geometry is carefully optimized. Similarly (Kohli et al., 2023), demonstrate BEOL-formed amorphous silicon grating couplers with metallic back reflectors on top of SiN platform. These examples illustrate that BEOL dielectrics and metals must be included explicitly in SWG design workflows.

Finally, SWG components require dedicated test access, calibration structures and process-monitor devices to qualify their performance across wafers (Bock et al., 2010). fabricate SWG straight waveguides of multiple lengths and use them to extract propagation loss and group index under a fixed process, while (Schmid et al., 2008) et al. employ SWG facets and SWG fiber-chip couplers as test structures to measure facet reflectivity and coupling efficiency. In both cases, SWG-specific monitors complement conventional strip and rib waveguide monitors and are essential for calibrating SWG effective index, loss and dispersion. For monolithic and hybrid integration flows, including such SWG test structures alongside standard process-control monitors is therefore critical for assessing how shared CMOS processes and BEOL stacks affect SWG performance.

For SWG-based devices, the constraints are summarized as follows:

• Etch depth (ED) and minimum feature rules limit attainable SWG duty cycles and fill factors, constraining the range of effective indices and anisotropies that can be realized.
• Extensive physical characterization is needed to understand fabricated versus schematic shape variations (Chen et al., 2013).
• Requirement of stochastic wafer-maps for each foundry to counteract process variations (Xing et al., 2022).
• Careful optimization of BEOL dielectric materials as it modifies vertical confinement and cladding indices, altering SWG effective index and dispersion.
• Heater placement and electrical routing near segmented or periodically structured waveguides must be designed to avoid strong local thermal gradients.
• Metal proximity can change local effective indices and increase cross-talk.
• SWG-specific process-monitor and test-access structures (e.g., SWG waveguide lines with varying duty cycle and period) are required in addition to conventional strip and rib monitors to qualify SWG performance across wafers.
• Standard design-rule-checking (DRC) tools optimized for Manhattan-style geometries perform poorly on SWG layouts. Curvilinear layouts increases layout file size tremendously (Bogaerts et al., 2014).
• Environmental sensitivity and packaging requirements vary by device class and architecture. Fully clad SWG communication and power-splitting devices can often use standard telecom-grade packaging, whereas exposed SWG-based sensors may require more stringent environmental control like hermetic packaging.

5.2 Cost and complexity drivers

In addition to the technical challenges discussed above, the development and commercialization of SWG-based photonic devices are often limited by cost and complexity. Many aspects of the design and manufacturing workflow require specialized expertise, equipment, and infrastructure. Figure 6a taken from (Latkowski et al., 2019) shows that the packaging, testing and assembly of a PIC make up 82% of total manufacturing cost. The testing and lithography costs are probably higher for SWG devices. The high cost for testing can be reduced considerably after standardization of testing infrastructure. Figure 6b shows the exponential reduction in overall wafer fabrication costs as the number of wafer orders increases assuming the volume of silicon-photonic chips in the fab is large enough to maintain a standardized process flow (Photonics Industries Association, 2024). The additional development steps for monolithic/hybrid integration increase costs, prolong development timelines, and ultimately delay time-to-market. For example, custom optical probes and wafer-level testing systems are frequently needed to characterize SWG devices, adding significant non-recurring engineering (NRE) costs. Improving device yield also requires extensive design of experiments (DOE) studies and process-corner characterization, which can substantially extend development timelines.

Another important challenge is the development of PDKs. Although PDKs are essential for enabling scalable and reproducible design, creating and validating accurate device models requires considerable fabrication and characterization effort. Furthermore, making PDKs acceptable across different foundries would help to increase manufacturing volume. In addition, many electronic design automation (EDA) tools were originally developed for conventional Manhattan-style layouts and often require customization to support SWG geometries, as well as associated DRC and layout-versus-schematic (LVS) verification. Together, these factors increase development costs and slow the transition of SWG technologies from research laboratories to commercial products. Fabrication tolerance optimized design with wafer map data would be a potential solution to increase yield. Similarly, wafer-level testing using standardized fiber-chip coupling solutions would enable rapid verification of wafers and devices and further reduce costs. Figure 7 illustrates a roadmap with key requirements necessary in Electronic-Photonic Design Automation (EPDA) software to help engineers efficiently design, test and send the PIC layouts to the foundry. The text in slanted red font highlights the development milestones which requires effort from EPDA software vendors to address. This roadmap was developed by (Photonics Industries Association, 2024) for silicon photonics in general but has been modified for commercializing SWG-based designs. The most critical challenges (highlighted in red) are in co-design and optimization of electronics and optics, improved verification capabilities (post-layout simulation, LVS, Design for Test (DfT)) and system-level analysis with multi-physics models for thermal and mechanical effects after packaging.

6 Interdisciplinary collaboration and commercialization pathways

SWG-based devices have been used in a wide variety of interdisciplinary applications, demonstrating the versatility and impact of this technology beyond traditional photonic integrated circuits. One of the most active application areas is label-free biological and chemical sensing, where SWGs enable enhanced light-matter interaction and increased sensitivity through engineered optical confinement and evanescent field control. Micro-ring resonator-based sensors employing SWG have been demonstrated in many works (Ning et al., 2023; Yan et al., 2017; Cheng et al., 2024; Flueckiger et al., 2016). Other SWG-based devices sensing platforms, including Bragg gratings (Luan et al., 2019) and coupled SWG waveguides (Ahmed et al., 2024), have demonstrated promising performance for refractive-index and environmental sensing.

Beyond sensing, SWGs have become important building blocks in optical communication systems (Chen et al., 2019). Their ability to engineer dispersion, effective refractive index, and modal properties has enabled a wide range of telecommunication components, including high data-rate waveguides (Gao et al., 2017), fiber grating couplers (Sunwoo et al., 2025; Fraser et al., 2025), multiplexers (Naghdi and Chen, 2018; Hao et al., 2020), and numerous other passive and active photonic devices (MacKay et al., 2022; Fraser and Ye, 2023; Khajavi et al., 2024). These diverse applications highlight the potential of SWG technology to address challenges across fields such as healthcare, environmental monitoring, and data communications.

Despite these advances, the path from laboratory demonstrations to commercial products remains challenging. One major challenge is technology transfer of academic research to industry. Bridging this gap requires strong partnerships among universities, research institutions, foundries, and industry stakeholders to accelerate device maturation, standardization, and large-scale deployment. Some organizations involved in building these partnerships and supporting the growth of the silicon photonics ecosystem include AIM Photonics, CMC Microsystems, and SiEPIC in North America; ePIXfab, IMEC, and CEA-Leti in Europe; and PETRA, IME, and CUMEC in Asia. Figure 8 includes a roadmap showing our proposed flow from lab prototype towards high-volume manufacturing of SWG-based devices.

The availability of foundry services capable of fabricating SWG devices is another critical factor in the commercialization of SWG technologies. Accessible fabrication platforms enable researchers and companies to prototype, validate, and scale new devices without the substantial capital investment to establish dedicated manufacturing facilities. Over the past decade, a number of academic and commercial foundries have expanded their silicon photonics capabilities, providing increasingly mature fabrication processes and design support. Table 2 lists a number of foundries involved in silicon photonics fabrication, together with their locations and available fabrication platforms. Drawing on the validation, standardization, manufacturing, integration, and commercialization challenges discussed throughout this review, Figure 9 presents an overarching roadmap for the development of scalable SWG technologies. The roadmap distinguishes current capabilities from emerging developments and longer-term manufacturing requirements across lithography, process uniformity, design-for-manufacturability, prototyping, testing, packaging, and cost scaling. The projected stages should be interpreted as indicative technology-readiness targets rather than fixed implementation timelines, since progress will vary across material platforms, foundries, and application areas.

TABLE 2. Silicon-photonic foundry services.

7 Conclusion

This paper has critically reviewed current key challenges and emerging research opportunities associated with translating silicon-based SWG devices from laboratory demonstrations to reproducible, scalable, and commercially deployable technologies. Unlike previous reviews focused primarily on SWG physics and device performance, this review connects fabrication-aware design and experimental validation with benchmarking, foundry qualification, testing, packaging, and commercialization.

A central conclusion is that high performance in an individual device is insufficient to establish manufacturing readiness. SWG technologies must also demonstrate dimensional tolerance, repeatability across dies and wafers, compatibility with foundry design rules, and reliable performance under process and environmental variations. To support reproducibility and meaningful comparison, we have proposed a minimum reporting set covering device geometry, fabrication conditions, simulation and measurement methods, uncertainty, and tolerance analysis.

Future progress will require SWG-specific process statistics, compact models, parameterized cells, process-monitor structures, and standardized testing practices. Integrating these capabilities with fabrication-aware design, wafer-level validation, and electronic–photonic design automation will help improve yield and shorten development cycles.

Continued advances in silicon photonics foundry services, design automation tools, fabrication-aware design techniques, and industry–academic collaboration are steadily reducing many of the barriers discussed in this review. Addressing the remaining challenges will enable SWGs to evolve from highly customized research structures into reliable and reusable photonic building blocks, supporting their broader adoption in future communications, sensing, computing, quantum technologies and other emerging integrated photonic applications.

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Footnotes

Edited by: David González-Andrade, University of Malaga, Spain

Reviewed by: Raquel Fernández De Cabo, The Institute of Photonic Sciences (ICFO), Spain