Symmetric pulse-enabled highly linear analog switching in ALD-grown HfO 2 /Ta 2 O 5 -based memristor for multi-level storage and synaptic applications

1 Introduction

The complementary metal-oxide-semiconductor (CMOS)-compatible Internet of Things (IoT) is pushing the boundaries of von Neumann systems to their technological limit (Moon et al., 2017). The increase in data generation by edge devices and web systems needs real-time data processing, which has instigated a new paradigm of data-centric computing (Riesenhuber and Poggio, 1999). The latency caused by the memory-bandwidth bottleneck of conventional computing systems faces a critical challenge to perform such data-centric computing in existing establishments (Patel et al., 2022). Artificial neural network (ANN) attracts extensive scientific evaluation for brain-inspired energy-efficient data processing to overcome the von Neumann bottleneck in traditional computing systems (Sun X. et al., 2025; Kim et al., 2021; Ielmini and Wong, 2018; Padovani et al., 2018; Pal et al., 2023). In recent years, a growing number of studies have concentrated on in-memory computing (IMC) employing the low-power emerging non-volatile memories (eNVMs), which can be deployed in a wide range of advanced and intelligent applications, including customized feedback therapy, high-speed communication, and visual recognition systems (Ohno et al., 2011; Ambrogio et al., 2018; Xu et al., 2014; Wang et al., 2018). Among the various eNVMs, memristor demonstrates significant advantages in meeting the requirements of next-generation hardware-based neuromorphic computing and Internet of Things (IoT) applications due to its non-destructive readout capability, high-density integration, fast switching speed, low-power consumption, including excellent scalability and strong compatibility with CMOS technology (Ielmini and Wong, 2018; Waser and Aono, 2007). Transition metal oxide (TMO), including SiO₂, Y₂O₃, ZrO₂, TiO₂, Al₂O₃, Ta₂O₅, and among various TMO materials (Illarionov et al., 2020; Wei et al., 2008; Yu et al., 2010; Sakamoto et al., 2007; Kumar et al., 2022; Wang et al., 2025), HfO_x-based memristors (Kumar et al., 2025a; Kumar and Rani, 2025; Ryu et al., 2021) devices exhibit outstanding performance characteristics, such as robust endurance, reliable data retention, ultrafast switching speed (∼ns), and excellent compatibility with state-of-the-art CMOS technology (Chen et al., 2009; Chen et al., 2012). The memristive devices have excellent potential for hardware-based neuromorphic computing due to their CMOS compatibility, low variation, reliable analog switching, and effective conductance state modulation (Zhang et al., 2019; Pal et al., 2022a; Shang et al., 2017; Sun B. et al., 2025). However, variability in resistive switching across repeated switching remains a critical challenge in memristive devices (Pal et al., 2022b; Acal et al., 2024; Avila et al., 2025; Pal and Wang, 2020). Therefore, effective control of the statistical variation in switching properties during repeated switching cycles is essential for reliable device operation.

This work extends our previous report with the bilayer memristor fabricated on 6-inch wafer with HfO₂ as the switching layer and tantalum oxide (Ta₂O₅) as a thermal-enhanced layer (TEL) (Kumar et al., 2025a). The device shows ultra-low device variation, including multilevel (MLC) data storage of 2-bit/cell and excellent electrical reliability, WRITE endurance ∼10⁵ cycles, and good data retention capability of 10⁴ s at room temperature (RT) with a memory window greater than 5 as compared to our previous report. The fabricated device exhibited high linearity 0.07 and symmetrical long-term potentiation and depression phenomena with a symmetrical pulse of 1 ms. Nevertheless, the fabricated devices are sensitive towards the pulse width (PW) and exhibit a significant change of >10–15% in the device resistance even under a PW of 100 µs. The fabricated devices demonstrated significant potential for high-speed and low-power analog and neuromorphic applications.

2 Device fabrication process

Figure 1 depicts the step-to-step wafer-level fabrication procedure for HfO₂/Ta₂O₅-based memristive devices. The detailed fabrication steps has been discussed in our previous report (Kumar et al., 2025a; Kumar et al., 2025b). The device fabrication process was started with growing a 200 nm SiO₂ layer using thermal oxidation on the 6-inch silicon wafer, as shown in Figures 1a,b. Next, the wafer is cleaned with acetone and isopropyl alcohol (IPA) for 10 min to eliminate the dust particles and organic contaminants. After the cleaning process, bottom electrode (BE) patterns were employed using optical photolithography, and subsequently, a 50 nm TiN layer as a BE was sputtered at room temperature, as shown in Figures 1c–f. A thin switching layer of HfO₂ (∼8 nm) and an additional Ta₂O₅ layer (∼2 nm) were deposited via thermal atomic layer deposition (ALD) without breaking the vacuum, as shown in Figure 1g. The temperature of the ALD chamber was maintained at 300 °C during the deposition cycles. The HfO₂ layer was grown using tetrakis (dimethylamido)hafnium(IV) (TDMAHf) as the hafnium precursor, and pentakis (dimethylamido)tantalum was used as the tantalum precursor to the Ta₂O₅ layer. H₂O was used as the co-reactant. Following the deposition of the oxide layers, reactive ion etching (RIE) was performed to expose the contact pads for accessing the BEs, as depicted in Figures 1h–k. Subsequently, another photolithography step was carried out to pattern the 50 nm top TEs, as shown in Figures 1l–o. Figure 1p shows the final fabricated device structure in which the memory cell’s effective size is measured at (5 × 5 μm²).

3 Results and discussions

The electrical measurements were performed using a customized ArC ONE memristor testing tool, in which BE is fixed to ground, and TE is connected to the voltage supply. The compliance current (I _CC) was fixed at 1 mA during all measurements. Initially, the bilayer pristine device was in the high resistance state (HRS), with the resistance in the range of sub-GΩ, and therefore, an essential electroforming process (V _f = +5.5 V) was executed to obtain the switching response. Figure 2a shows a 6-inch Si wafer, which has thousands of memristive devices in both standalone as well as crossbar array arrangements. Herein, standalone devices were electrically characterized. Figure 2b exhibits the resistive switching response of the first 50 cycles of the memristor after an electroforming event, in which, under the application of voltage from 0 to +4 V, the device is switched from the HRS to the low resistance state (LRS) and shifted to the SET process at V _SET = +3.06 V. Similarly, under the application of voltage from 0 to −4 V, the device is switched back from the LRS to the HRS and transited to the RESET process at V _RESET = −3.2 V. The current-voltage (I-V) scan direction during switching responses has been indicated in Figure 2b with blue arrows that clearly demonstrate the non-volatile nature of the fabricated device.

The resistive switching mechanism in the memristive devices is associated with the formation and rupture of conductive filaments (CFs) in association with oxygen ion migration under the influence of applied electrical potential (Dahiya et al., 2025). Herein, Figure 2c also describes the dominating resistive switching mechanism in the fabricated devices. Figure 2c shows, the transport mechanism was primarily analyzed through detailed log–log(I–V) curve fitting across different voltage regions. The conduction mechanism has been consistent using the fitting of the memristor device under LRS and HRS regions, respectively. Linear fits at multiple regions are applied to each dataset to determine the slopes corresponding to the respective conduction mechanisms. The In the LRS, current exhibits a nearly linear dependence on the applied voltage in both low-field (Slope∼1.08) and high-field (Slope∼1.16) region. This linear relationship confirms Ohmic conduction, which is attributed to the formation of conductive filaments during the SET operation. In contrast, the HRS reveals voltage-dependent transitions between different transport regimes. The current behavior can be described by the empirical relation, I = α V 1.20 + β V 2.13 + γ V 16.6, where *α , β , γ* are fitting parameters. At low applied voltages, the double logarithmic I–V slope remains to unity, indicating Ohmic conduction dominated by thermally generated carriers. As the voltage increases, the slope exceeds 2.13 and 16.6, suggesting a transition to space-charge-limited-current (SCLC) conduction. In the high-field region, the transport is governed by trap-controlled SCLC, while Ohmic behavior in the low-field region. With increasing bias, enhanced electron injection and electric-field-driven migration O^2– ions facilitate carrier trapping at oxygen vacancy (V _*O*) sites and dopant-related defect states withing the switching layer. The insertion of a thin Ta₂O₅ layer, which can also act as the thermal-enhanced interfacial layer to improve the uniformity of oxygen vacancy distribution (Xiang et al., 2019; Wanga et al., 2021). The presence of this interfacial oxide layer significantly influences oxygen vacancy generation and filament evolution. During the SET operation under positive bias applied to the TE, O^2– ions migrate toward the electrode interface, contributing to the oxygen-deficient (V _*O*) region with in the HfO₂ layer to form a filamentary path. Repeated switching cycles further increase vacancy concentration, resulting in a defect-rich (V _*O*) switching layer. During the RESET process, the application of reverse bias induces recombination and redistribution of positively charged defect species, leading to filament disruption and restoration of the HRS. The device thus demonstrates bipolar resistive switching behavior (Pal et al., 2023). The reversible operation is associated with soft dielectric breakdown, which remains recoverable under controlled electrical stress (Dongale et al., 2015). were dominated, as shown in Figures 2d–f. The device performance under typical square pulses with different amplitudes and PW was also studied. The information was written in the memory cell using a SET pulse amplitude of +3.5 V with a PW of 1 ms, and data were erased from the memory cell using a RESET pulse amplitude of −3.5 V with a PW of 1 ms.

The device shows adequate P/E endurance of approximately 10⁵ cycles, maintaining the stable memory window, as shown in Figure 3a. The reliability performance of the memristor was further investigated by the long-term data retention capability of the device at RT, as shown in Figure 3b. The distinct HRS and LRS remained stable up to 10⁴ s without any significant degradation. Furthermore, the statistical distribution of the device-to-device (D2D) and cycle-to-cycle (C2C) variation depicted excellent uniformity with ultra-low variation. The D2D variation was verified on the randomly selected 25 devices in a single block on the 6-inch Si wafer.

The presence of a thermal layer improved the covariance value (σ/µ) at RT was obtained as 0.19 for HRS and 0.11 for LRS, as shown in Figure 4a. Similarly, the C2C variation has been verified using 100 repeated switching cycles. The σ/µ value was obtained as 0.12 for HRS and 0.09 for LRS, as shown in Figure 4b.

Nevertheless, the device reliability of the optimized device under study was further investigated by utilizing the analog behavior of the device and the multibit data storage capability. The multibit data storage functionality (MLC) was confirmed by the four distinct resistance levels employing data retention capability of 2-bit/cell for 10⁴ s of each conductance state using different V _RESET ranging from 4.0 V to 3.0 V with an interval of 0.5 V, as shown in Figure 5a. The four programmed resistance states of ∼119.34 kΩ, 84.64 kΩ, 52.2 kΩ, and 18.87 kΩ exhibit adjacent resistance ratios of 1.42, 1.62, 2.89, ensuring clear level separation. All states remain stable up to 10⁴ s under low read bias without observable overlap, including minimal short-term read disturb. Similarly, the pulse parameters, such as amplitude, width, and number of pulses, were optimized to achieve a stable analog-type switching response and enhance the overall device reliability.

The PW is the critical parameter to define how quickly the device can switch between two stable states (Lim et al., 2025). Therefore, reducing the PW width remarkably decreases the energy consumption of the device during operation and increases the computational speed of the device. Furthermore, the impact of the PW was investigated on the fabricated memristive devices, and the overall percentage change in the device conductance was measured. Figure 5b shows the overall change in the device conductance under different PWs from 2 ms to 100 µs. The device exhibits an approximate 17%–20% change in the device conductance under the application of 10 pulses of PW of 2 ms, and pulse amplitude ±6 V because comparatively higher input voltages are required in a set of a few pulses as it exhibits overall changes in the device resistance. Additionally, switch seeker functionality requires extensive pulse parameter optimization with an appropriate amount of percentage tolerance. The number of pulses, pulse amplitude, and PW were kept constant for all measurements. Similarly, the device shows 15%–17% and 12%–15% change in the conductance for the PW of 1 ms and 100 µs, respectively. Herein, it is observed that the larger PW can be associated with the generation of an overall electric field in the device as well as induced Joule heating. While a shorter PW leads to lower Joule heating effect, that can certainly affect the overall change in the device resistance. The controlled analog switching behavior emulates the biological synapse response, where the gradual tunable synaptic weight is essential to develop the neuromorphic hardware (Yoon et al., 2023).

The HfO₂/Ta₂O₅ bilayer memristive crosspoint device was further explored to confirm its potential application in the synaptic impulse transmission. A schematic analogy of a biological neuron and a memristor device-based artificial synapse is illustrated in Figure 6a. The highly linear potentiation and depression responses were observed using the symmetric pulse train of consecutive 50 SET and 50 RESET pulses with 1 ms PW, as shown in Figure 6b. The designed SET and RESET pulses of amplitude ±3.0 V and 1 ms PW were employed to investigate the entire synaptic behaviour. The repeatability of the long-term potentiation (LTP) and long-term depression (LTD) with the aforementioned symmetric pulse configuration has been achieved by applying consecutive 1000 SET and RESET pulses, maintaining a consistent conductance level as shown in Figure 6c. The device non-linearity (NL) factor value was calculated to observe the effects in the artificial neural network (ANN), an essential parameter for the neuromorphic computing (Gutsche et al., 2021; Wang et al., 2019). The NL factor was then calculated by using Equation 1, as the average absolute deviation between the normalized conductance and the ideal linear response across the full pulse sequencewhere N is the total number of the applied pulses, G _*norm*(n) is the normalized conductance at the nth pulse, and G _*ideal*(n) represents the ideal linear conductance update (Shooshtari et al., 2025; Choi et al., 2020). This approach evaluates the deviation from ideal linear weight modulation over the entire potentiation/depression cycle. An ultra-low NL has been achieved to NL _*avg* = 0.07 using a symmetric pulse scheme as shown in Figure 6b. The present study focuses on device-level electrical characterization and mathematical extraction of the NL factor along with single-device analysis to elucidate the switching mechanism. In large-scale crossbar arrays, sneak-path currents may degrade read accuracy, and practical implementation would require selector integration through 1S1R or 1T1R architecture to suppress leakage paths. The low operating current demonstrated here suggests compatibility with transistor-assisted configurations. The system-level neural network validation and array-level integration addressing sneak-path effects will be pursued in our future work. Moreover, the experimental results confirmed the proposed synaptic applicability of the fabricated HfO₂/Ta₂O₅ bilayer memristor device in CMOS-compatible neuromorphic hardware.

N L = 1 N ∑ n = 1 N G n o r m n − G i d e a l n (1)

4 Conclusion

In summary, HfO₂/Ta₂O₅-based bilayer memristive devices were fabricated using a single thermal ALD system on a Si substrate at a temperature of 300 °C. The fabricated devices emulated a stable bipolar resistive switching response of program/erase endurance of 10⁵ switching cycles after the essential electroforming process, showing the potential of the memristor in eNVM applications. Additionally, the fabricated devices effectively maintained their distinct resistance states beyond 10⁴ s along with multibit (MLC) data storage of 2-bit/cell, indicating high-density data storage applications. The fabricated devices also efficiently emulated synaptic functionalities and exhibited highly linear and symmetrical long-term potentiation (LTP) and long-term depression (LTD) phenomena, including an ultra-low NL value of 0.07 using a symmetrical pulse of 1 ms. Finally, the effect of PW on the overall change in the device resistance was demonstrated, in which a large PW results in a greater change in the device resistance that can be associated with the generated Joule heat during operation. The fabricated bilayer memristor has potential for BEOL-compatible future energy-efficient high-density storage and synaptic device for the realization of neuromorphic hardware.

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Footnotes

Edited by: Zeinab Ramezani, University of Miami, United States

Reviewed by: Jiyong Woo, Kyungpook National University, Republic of Korea

Mohsen Mahmoudysepehr, University of Waterloo, Canada