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Frontiers in Nanotechnology ·

Volume 8 - 2026 | https://doi.org/10.3389/fnano.2026.1823858

Tenfold power consumption reduction in reconfigurable nonlinear-processing units through capacitive control

  • R. J. C. Cool1,2
  • L. Kingma1
  • W. G. van der Wiel1,2*corresponding author
  1. 1NanoElectronics Group, MESA+ Institute and BRAINS Center for Brain-Inspired Computing, University of Twente, Enschede, Netherlands
  2. 2Institute of Physics, University of Münster, Münster, Germany
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Abstract

Reconfigurable nonlinear-processing units (RNPUs) are silicon-based, multi-input-multi-output nanoelectronic devices that enable complex functionality and are promising building blocks for future brain-inspired computing hardware. However, in existing implementations, all electrodes draw current, resulting in substantial power dissipation. Here, we present a modified device design in which half of the electrodes are capacitively coupled to the silicon region through a dielectric layer, while the others are in direct electrical contact. This configuration allows electrostatic control of the potential landscape with minimal leakage current. We experimentally demonstrate all standard Boolean logic gates at room temperature consuming up to 10 times less power than reported for the original RNPU, which operated at 77K [Chen et al., Nature 577, 341 (2020)]. Simulations based on an RNPU surrogate model yield classification accuracies of 95.9% ± 0.2% for the MNIST handwritten digits dataset and 86.7% ± 0.2% for the FashionMNIST dataset with a similar reduction in RNPU power. These results demonstrate that capacitive electrodes provide an effective and energy-efficient means of controlling in-materia computing devices, opening a pathway for energy-efficient RNPU-based architectures.

Keywords

1 Introduction

Brain-inspired computing is an emerging technology that seeks to replicate key principles of neural information processing to achieve highly efficient, adaptive, and robust computation, with a strong emphasis on reducing power consumption for artificial intelligence applications (Jaeger et al., 2023; Kaspar et al., 2021; Zolfagharinejad et al., 2024).

Because biological neural systems inherently compute through the dynamics of physical processes rather than through abstract digital operations, this paradigm naturally converges with the broader concept of physical computing, which harnesses the intrinsic behavior of materials and devices to perform computation directly in hardware. In recent years, various electronic device concepts based on disordered networks have demonstrated energy-efficient computing capabilities (Bose et al., 2015; Chen et al., 2020; Dale et al., 2016; Milano et al., 2022; Studholme et al., 2023; Zhu et al., 2023). These devices leverage nonlinear and dynamic conduction mechanisms within multiterminal architectures. In contrast to conventional neuromorphic circuit approaches, which engineer predictable device physics within established integrated circuit-design frameworks (Douglas et al., 1995; Shibata et al., 1995; Zhang et al., 2024), these devices exploit material disorder and complexity as computational resources rather than treating them as design constraints (Jaeger et al., 2023; Kaspar et al., 2021). Several approaches exist for training such devices. In reservoir computing, the internal dynamics remain untrained, and only a linear readout layer is optimized (Jaeger, 2001; Nakajima et al., 2014; Stepney, 2012). Alternatively, in reconfigurable nonlinear-processing units (RNPUs, previously referred to as dopant network processing units or DNPUs) the internal state can be tuned via designated input, output, and control electrodes (Chen et al., 2020; Zolfagharinejad et al., 2025). By adjusting the voltages on the control electrodes, a complex electrical potential landscape is shaped across the conductive region, enabling rich, tunable input–output mappings. However, because the control electrodes are in direct electrical contact and conductive, the device typically draws substantially more current than is measured at the output electrode.

In this Article, we present a modified RNPU design: half of the electrodes are capacitively coupled to the silicon region through a dielectric layer, while the others are in direct electrical contact. This modified device design is referred to as ‘capacitive RNPU’ or ‘c-RNPU’. We operate the c-RNPUs at room temperature (Kareem, 2026; Zolfagharinejad et al., 2025) and evaluate their performance and power consumption on benchmark tasks, including Boolean logic emulation, MNIST digit recognition, and FashionMNIST classification. Boolean gate abundance serves as a measure of device tuneability, while circuit simulations trained on MNIST and FashionMNIST assess practical computational capabilities. Based on these simulations, we estimate the total energy efficiency. All results are compared to the original RNPU design (operated at 77K) by Chen et al. (2020). Our findings show that capacitive electrodes reduce power consumption by an order of magnitude or more, while preserving functionality, resulting in more energy-efficient RNPUs.

2 Fabrication and experimental procedures

2.1 Device fabrication

A 300 nm thermal oxide layer was grown on an n-type silicon substrate. Photolithography and wet etching were used to define 26 × 60 μm2 implantation windows, within which an additional 35 nm of oxide was thermally grown to act as a stopping layer. Boron atoms were implanted at an equivalent energy of 9 keV and a dose of 3.5 × 1014 cm-2. They were activated by rapid thermal annealing at 1,050 °C for 7 s. Due to the implantation from the top, the dopant density reduces gradually with depth. Four electrodes (1.5 nm Ti/25 nm Pd) with bonding pads were patterned using e-beam lithography. The samples were subsequently exposed to reactive ion etching using 25 sccm of CHF3, 5 sccm of O2 and a forward bias of 25 W, while keeping the pressure constant at 10 mTorr for 6.5 min. This etches down 90 nm of exposed silicon in the implantation windows. 20 nm of aluminum oxide was deposited at 250 °C using TMAH and H2O as precursors. A second layer of four electrodes was patterned using the same procedure as for the first layer. Finally, the device was annealed on a hotplate in atmospheric conditions to improve the interface between the channel and the dielectric. The temperature was gradually increased from 180 °C to 325 °C, with 5-min isothermal holds at 180, 220, 250, 280, 300 °C and a 10 min hold at 325 °C. A schematic of the fabrication procedure is given in Supplementary Figure S1.

2.2 Measurements

All measurements were carried out at room temperature in a custom metal enclosure that was continuously flushed by gaseous nitrogen. Voltages were applied to the electrodes using an NI-9264 from National Instruments. Current read-out was performed using I/V converters with a resistance of R = 5 M Ω attached to an NI-9202 module. We operated at input frequency f = 100 Hz and read-out frequency f = 10 kHz . A schematic of the measurement setup is given in Supplementary Figure S2.

2.3 Surrogate models

Surrogate models of the devices were created using the method described by Ruiz Euler et al. (2020). A digital neural network is trained with a large set of input-output data. The data is acquired by continuously monitoring the current through the output electrode, while applying triangle-wave voltage signals of varying frequencies to all input electrodes. The capacitive electrodes were swept across a voltage range from −6 V to +6 V with frequencies f 1 ≈ 47.0 mHz, f 3 ≈ 42.7 mHz, f 5 ≈ 53.3 mHz and f 7 ≈ 50.7 mHz. The conductive electrodes were meanwhile swept across a voltage range of -1V to +1V with frequencies f 2 ≈ 0.283 Hz, f 4 ≈ 0.372 Hz and f 6 ≈ 0.322 Hz. The frequencies were chosen to be slow enough that AC currents do not influence the measurements, and their relationship such that the entire input space is covered efficiently with minimal repetition.

The neural network model consisting of 7 inputs, 5 hidden layers containing 90 neurons SiLU was trained on this data using an AdamW optimizer with a learning rate of 1 × 10−5, weight decay of 1 × 10−6 and batch size of 128. The model was trained using a custom weighted squared-error loss, where prediction errors were normalized by the target magnitude plus a constant offset to improve relative accuracy at low-current values. An additional twofold penalty was applied to errors in the output channel to prioritize accurate functionality over accurate power consumption estimation.

3 Results and discussion

3.1 Device characterization

The c-RNPUs consist of a 300 nm diameter (Kareem, 2026) region in an n-type (100) silicon wafer doped with boron atoms using ion implantation followed by activation using rapid thermal annealing. Four Ti/Pd electrodes were evaporated directly on top of the doped substrate. Subsequently, the exposed doped Si was etched down by 90 nm using reactive-ion etching. This reduces the boron concentration to approximately 1018 cm-3 near the etched surface, while preserving a concentration of ∼1020 cm-3 directly beneath the electrodes. These values were estimated based on the ion implantation parameters (9 keV equivalent energy, 3.5 × 1014 cm-2 dose) in combination with the depth of the dry etching. The resulting root mean square roughness (R rms) of the etched surface is ∼10 nm. A 20 nm layer of aluminum oxide was deposited by atomic layer deposition (ALD) at 250 °C, well below the boron diffusion temperature. Another four Ti/Pd electrodes were deposited on top of the aluminum oxide, in between the already deposited electrodes, resulting in the 8-electrode geometry of Figure 1a, shown in the atomic-force-microscope image of Figure 1b. Due to reactive ion etching, the silicon crystal is damaged and its native oxide oxygen deficient (Oehrlein and Lee, 1987; Syau, 1992; Weman et al., 1990), likely causing a high density of both deep and shallow traps (e.g., Pb centers). To partially counteract this, the devices were annealed on a hotplate in atmospheric conditions. The annealing (180 °C–325 °C) increases the conductance and, more markedly, the transconductance (depicted in Supplementary Figure S3). This is consistent with a reduction in interface trap density, likely aided by the formation of a thin interfacial SiOx layer (Benick et al., 2010; Bhattacharjee and Kim, 2021; Huang and Chuang, 2021). We therefore attribute the improved field control to annealing-induced recovery of etch-related interface defects.

Device layout and characterization of a capacitive reconfigurable nonlinear-processing unit (c-RNPU) **(a)** Schematic circuit diagram (top) and side view (bottom) of a c-RNPU. **(b)** False-color atomic-force-microscope image of the eight electrodes surrounding the 300 nm diameter active region. The current-carrying electrodes (yellow) are elevated, whereas the capacitive ones (purple) lie lower due to deposition after reactive ion etching. **(c)** Current-voltage (*I-V*) characteristics of the current-carrying electrodes. The voltage is applied to the different electrodes, while the output current *I* <sub>out</sub> is measured using an IV-converter. All other electrodes are grounded. Inset: leakage current *I* <sub>leak</sub> of capacitive electrodes measured using the same procedure. **(d)** *I* <sub>out</sub> vs. *V* <sub>1</sub> for different values of *V* <sub>2</sub>. All other electrodes are grounded.
Figure 1. Device layout and characterization of a capacitive reconfigurable nonlinear-processing unit (c-RNPU) (a) Schematic circuit diagram (top) and side view (bottom) of a c-RNPU. (b) False-color atomic-force-microscope image of the eight electrodes surrounding the 300 nm diameter active region. The current-carrying electrodes (yellow) are elevated, whereas the capacitive ones (purple) lie lower due to deposition after reactive ion etching. (c) Current-voltage (I-V) characteristics of the current-carrying electrodes. The voltage is applied to the different electrodes, while the output current I out is measured using an IV-converter. All other electrodes are grounded. Inset: leakage current I leak of capacitive electrodes measured using the same procedure. (d) I out vs. V 1 for different values of V 2. All other electrodes are grounded.

We fabricated c-RNPUs across multiple independent chips and confirmed that the key device characteristics are reproducible. Full computational benchmarking was performed on two devices, whose results are in good agreement. The main quantitative results presented below are from a single device for numerical consistency, while the results of the validation device are presented in Supplementary Figure S4. During all electrical measurements, the substrate was electrically floating, while the output electrode was held at virtual ground via a transimpedance (current-to-voltage) amplifier. Furthermore, the setup was continuously flushed with nitrogen gas during all measurements, which proved crucial for preventing bias stress caused by the relatively high voltages applied to the capacitive electrodes. Bias stress in transistors with oxide gate dielectrics has previously been attributed to water-mediated proton migration (Ding et al., 2022; Iqbal et al., 2021; Sharma, 2011). Consistent with this mechanism, we tentatively attribute the observed drift to hydrogen-containing species generated through electrochemical reactions involving residual water at the high-voltage capacitive electrodes, although a detailed mechanistic study is beyond the scope of this work.

The nonlinear response of the current-carrying electrodes is shown in Figure 1c. The leakage current of the capacitive electrodes is displayed in the inset. The leakage current is on the order of tens of femtoamperes, negligible compared to the nanoampere-level currents in the conductive electrodes. The capacitive electrodes exhibit significant transconductance (i.e., modulation of the output current as a function of voltage applied to a capacitive electrode) when the channel is defined by the neighboring current-carrying electrodes, as shown in Figure 1d. Capacitively modulated current curves for all two electrode combinations are displayed in Supplementary Figure S5.

In general, the behavior of the capacitive electrodes is as expected. Positive voltages reduce the current through the channel underneath, akin to a p-type MOSFET. The device requires comparatively higher voltages to induce a relatively weak field effect, which we attribute to several factors. Firstly, the channel is poorly defined and the capactive electrode does not fully cover the channel. Furthermore, the Si-AlOx interface is rough due to the dry etching step, causing a high density of interface states (Erzgräber et al., 1997; Ragnarsson and Lundgren, 2000; Weman et al., 1990). The effect of applying voltage to a capacitive electrode that is not located directly on top of the channel sometimes shows an inversed field effect, i.e., the current in the channel goes up when increasing the voltage. This is observed in Supplementary Figure S5. In these cases, the current from the biased electrode is diverted to other current-carrying electrodes instead of the designated output. This capacitively induced behavior effectively gives rise to negative differential resistance (NDR), which is known to be crucial for nontrivial functionality in RNPUs (Chen et al., 2020). We note that the voltage range used for the capacitive electrodes in this study (−6 V–6 V) is higher than would be desirable for future applications, which typically require integration with CMOS. This should be viewed as a technical limitation of the present device implementation rather than a fundamental constraint of the concept.

Analysis of the effects of the capacitive electrodes on transport follows, while a full comprehensive analysis of non-equilibrium transport resulting in the observed nonlinear IV-characteristics is beyond the scope of this work. In forthcoming work (Kareem et al., manuscript in preparation), we show that transport in room-temperature RNPUs is governed by dopant- and trap-mediated space-charge effects. In this framework, RIE-induced interface traps suppress the equilibrium carrier density, while ionized dopants and injected carriers shape the space-charge distribution and electric-field profile. That study also examines how the active-region diameter controls the onset and strength of nonlinear transport, showing that the present 300 nm geometry provides a suitable operating regime for tunable, CMOS-compatible voltages on the conductive electrodes.

Field-effect characteristics were measured across 12 devices from 3 independently fabricated chips to establish reproducibility (Figure 2a). Significant gate modulation is observed across all devices, with device-to-device variability attributed to lithographic misalignment between the two electrode layers. This misalignment creates an imbalance in the coupling efficiency of individual capacitive electrodes, resulting in a spread of field-effect strengths within and across devices. Balanced devices were chosen for benchmarking and simulations.

**(a)** Normalized field-effect across various devices and chips. Individual measurements shown in light grey. Inset: Measurement configuration using three neighboring electrodes in c-RNPU. Other electrodes are grounded. **(b)** Activation energies were extracted as a function of gate voltage over 280–320 K. The orange dots represent the datapoints, and grey bars represent 95% confidence interval. Black dashed line serves as a guide for the eyes. Inset: Schematic of top view of the test structure that was used for this measurement. The electrodes create a 10 μm × 14 µm channel. The gate is centered around the middle of the channel covering 8 µm of the 10 µm channel. **(c)** IV-characteristic for different gate voltages in a test structure. Three regimes can be identified: ohmic, saturation and recovery. Inset: Scanning electron microscope image of the test structure, consisting of a 26 μm × 26 µm channel, of which the centered gate fully covers 20 µm. **(d)** Log-log plot of a selection of the IV-curves shown in **(c)**. Slopes *m =* d log I d log ⁡ V are marked by black lines.
Figure 2. (a) Normalized field-effect across various devices and chips. Individual measurements shown in light grey. Inset: Measurement configuration using three neighboring electrodes in c-RNPU. Other electrodes are grounded. (b) Activation energies were extracted as a function of gate voltage over 280–320 K. The orange dots represent the datapoints, and grey bars represent 95% confidence interval. Black dashed line serves as a guide for the eyes. Inset: Schematic of top view of the test structure that was used for this measurement. The electrodes create a 10 μm × 14 µm channel. The gate is centered around the middle of the channel covering 8 µm of the 10 µm channel. (c) IV-characteristic for different gate voltages in a test structure. Three regimes can be identified: ohmic, saturation and recovery. Inset: Scanning electron microscope image of the test structure, consisting of a 26 μm × 26 µm channel, of which the centered gate fully covers 20 µm. (d) Log-log plot of a selection of the IV-curves shown in (c). Slopes m = d log I d log ⁡ V are marked by black lines.

Field-effect-transistor-like test structures were fabricated using the same fabrication procedure as c-RNPUs and analyzed to determine the activation energy as a function of applied electric field on the gate (Figure 2b). Activation energies were extracted from the zero-bias conductance using the Arrhenius temperature dependence (Sze and Ng, 2007):where σ(T) is the temperature-dependent conductivity, σ 0 a constant factor, E a the activation energy, T is temperature and k B the Boltzmann constant. In this model the activation energy is equal to the distance between the Fermi energy and the mobility edge corresponding to the majority carrier.

σ T = σ 0 e − E a / k B T (1)

The Fermi level is positioned deep inside the gap, which we attribute to defect states that result from the dry-etching step in fabrication (Oehrlein and Lee, 1987; Syau, 1992; Weman et al., 1990). Using Equation 1, we find that E a = 0.38 ± 0.05 eV at room temperature and that it is tunable by the gate from 0.35 ± 0.01 eV to 0.45 ± 0.01 eV. The extracted activation energy is consistent with the expected offset between the valence band and the Fermi level in a p-type, trap-dominated system (Sze and Ng, 2007). Based on the found Arrhenius dependence of the conduction and the corresponding activation energy and its gate tuneability, we infer that the device is in a regime of strong Fermi-level pinning and corresponding low free carrier density.

The effective gate coupling in the c-RNPU is reduced well below that of a conventional MOS geometry by several compounding factors: the capacitive electrode covers only a fraction of the active region, the channel lacks counter-doping and therefore has no well-defined depletion layer beneath the gate, and confinement in the depth direction is weak, with the channel extending until a soft pn-junction boundary. Together these factors dilute the gate field over a large volume. An effective coupling factor α = d E a e d V G , where V G is the applied gate voltage, is extracted from the gate-voltage dependence of the activation energy (Figure 2b) and yields values in the range of 5 × 10−3 to 3 × 10−2, consistent with this highly non-ideal gate geometry. The nonlinear relation between E a and V G reflects the nonlinear electrostatic response of the channel to the gate field. The gate-dependent activation energy is consistent with a shift of the Fermi level relative to the trap band, modulating carrier injection through the potential landscape rather than directly changing the trap configuration.

At higher fields transport through the conductive electrodes is subject to nonlinear electrostatic effects that are also commonly observed in field-effect transistors. At high source–drain bias, the current approaches a plateau (saturation), which we attribute to depletion near the drain contact (Figure 2c). The behavior is asymmetric: for positive bias the current increases again (recovery) after the initial saturation. This is more evident in the log–log comparison of both bias polarities (Figure 2d). Slopes m = d log I d log ⁡ V corresponding to three regimes are identified and marked by black lines. At low bias, m = 1 for all gate bias values, clearly marking an Ohmic regime. For negative source-drain bias slopes drop to m = 0.2, indicating saturation. For the other polarity m increases as the drain voltage now enhances the channel’s conduction. We attribute the renewed increase in current under positive bias to enhanced carrier injection at the contact.

Saturation behavior is caused in c-RNPUs by drain-side depletion, which is the reduction of free carriers near the drain contact of a semiconductor device caused by band bending under an applied bias. As the local potential increases, carriers are repelled or trapped, leading to a region with reduced conductivity that limits current flow. Similarly, current can become enhanced by band bending in the opposite direction. More generally, nonlinear transport effects are caused by the interplay of electrostatics and a tunable trap-dominated channel. These nonlinearities are beneficial in achieving nontrivial functionality in RNPUs (Chen et al., 2020; Tertilt et al., 2022).

3.2 Functionality and energy consumption

Two input modes are considered. In the first, two capacitive electrodes opposing the output electrode are used as inputs, see Figure 3a (left). This mode is of special interest, as this is the first time capacitive electrodes are used as inputs. In the second mode (Figure 3a, right), we use conductive inputs, leaving only one conductive electrode for control, and a large part of the tuning to the capacitive electrodes.

c-RNPUs were trained to emulate Boolean logic gates under two distinct input configurations. **(a)** Left: Schematic of Configuration 1, in which two capacitive electrodes serve as inputs. Input and output contacts are marked with orange dots and a green square respectively; voltages on other contacts were optimized by a genetic algorithm. Middle: Schematic binary representation of the input voltage sequence on the input electrodes over time. Rise and fall times have been omitted. Right: Configuration 2, in which two current-carrying electrodes serve as inputs. **(b)** Output current for Configuration 1, implementing an XOR gate. The binary states represent input voltages V in , 1 = −6 V, 6 V and V in , 2 = −6 V, 6 V in this configuration. **(c)** Output current for configuration 2, implementing an XNOR gate. The binary states represent input voltages V in , 1 = −0.7 V, 0.95 V and V in , 2 = −0.9 V, 0.22 V. **(d)** Power consumed by electrodes 2, 4 and 6 across the four input states in **(b)**. **(e)** Power consumed by electrodes 2, 4 and 6 across the four input states in **(c)**.
Figure 3. c-RNPUs were trained to emulate Boolean logic gates under two distinct input configurations. (a) Left: Schematic of Configuration 1, in which two capacitive electrodes serve as inputs. Input and output contacts are marked with orange dots and a green square respectively; voltages on other contacts were optimized by a genetic algorithm. Middle: Schematic binary representation of the input voltage sequence on the input electrodes over time. Rise and fall times have been omitted. Right: Configuration 2, in which two current-carrying electrodes serve as inputs. (b) Output current for Configuration 1, implementing an XOR gate. The binary states represent input voltages V in , 1 = −6 V, 6 V and V in , 2 = −6 V, 6 V in this configuration. (c) Output current for configuration 2, implementing an XNOR gate. The binary states represent input voltages V in , 1 = −0.7 V, 0.95 V and V in , 2 = −0.9 V, 0.22 V. (d) Power consumed by electrodes 2, 4 and 6 across the four input states in (b). (e) Power consumed by electrodes 2, 4 and 6 across the four input states in (c).

All electrodes not designated as input or output are used as control electrodes to obtain a desired input-output functionality. Using a genetic algorithm (Goldberg and Holland, 1988) to train the control voltages, all Boolean gates were realized in both input modes (Chen et al., 2020; Ruiz Euler et al., 2020). The binary input states are represented by designated values of input voltages V in , 1 and V in , 2 and applied to the device in a sequence of four combinations, displayed in Figure 3a. (middle). The generated sets of genes correspond to the voltages that are to be applied to the control electrodes. The values for the input voltages are untrained. Each genome is evaluated by measuring the signal that results from applying the given input sequence, while applying these control voltage values. Every generation each set of genomes is ranked their fitness value F using the fitness function:where m and c are fitting parameters of the linear fit I out V in , 1 , V in , 2 = m G V in , 1 , V in , 2 + c with G V in , 1 , V in , 2 representing the truth table of the logic gate.

F = m M S E + k c , (2)

We use 26 genomes, of which the elite (highest scoring) four stay unchanged and the remaining 22 genomes are generated by stochastic universal sampling (Baker, 1987) and mutated by a dynamic mutation rate that starts at 0.31 in the first generation. The algorithm was implemented using the Python brains-py library (Alegre-Ibarra et al., 2023).

Examples of an XOR gate and an XNOR gate in Configurations 1 and 2 are given in Figures 3b,c, respectively. The input voltages used are given in the caption. Figures 3d,e show the power consumed by all conductive electrodes for the four Boolean input configurations. The total power consumption P is calculated as follows:where V *i* and I *i* denote the voltage at, and the corresponding current through, electrode i, respectively.

P total = ∑ i ∈ 2 , 4 , 6 V i I i , (3)

Individual electrodes can exhibit negative power consumption, indicating that they extract energy from the device rather than supply it. However, the total power consumption summed over all electrodes remains strictly positive. To determine the total power of a given logic gate, we average the power consumption across its four two-input states.

The conductive electrodes are operated such that the current through them never exceeds 350 nA. The output current is typically a few tens of nanoamperes. Given that the leakage current through the capacitive electrodes remains below a few tens of femtoamperes and the applied voltages are on the order of a few volts, their total power consumption stays well below 1 nW. Their contribution to the total power consumption can therefore be neglected.

The number of Boolean gates a device can realize for a given input-output configuration is a measure of its computational capacity (Tertilt et al., 2022) that has been used in the past and therefore allows for comparison (Ruiz Euler et al., 2020).

Figure 4 shows the number of Boolean gates and their corresponding energy consumption for the two input configurations considered for a c-RNPU (Figures 4a–d), and, for comparison, two configurations for all-conductive RNPUs (Figures 4e–h). The two-input combinations 00,01,10,11 were fed into the device for a set of 10,000 randomly generated control voltage combinations. The fitness F of the resulting output currents was calculated for each Boolean gate using Equation 2, and the corresponding power consumption using Equation 3. To investigate whether the device has similar functionality as a traditional device and to ultimately compare their power consumption, the experiment was repeated on a device with only current-carrying electrodes (Figures 4e–h). This device was fabricated identically to the c-RNPU but etched approximately 10 nm deeper, bringing the operating currents into a comparable range and ensuring a fair comparison. At equal etch depth, all-conductive devices exhibit higher current levels due to the larger number of conductive electrodes and the reduced spacing between them. Note that this device differs from the original RNPU presented by Chen et al. (2020) as that was designed to operate at 77K, while all experiments in this paper were performed at room temperature (Chen et al., 2020; Kareem, 2026).

Functionality and power consumption comparison between capacitive and fully conductive RNPU for two input configurations. **(a)** Abundance of Boolean gates in Configuration 1 as a function of desired fitness in 10,000 randomly sampled control voltage combinations. Error bars represent 95% confidence values (Clopper and Pearson, 1934), representing the range where the true mean is likely to fall. **(b)** For each Boolean gate, energy costs for a single operation of all control voltage combinations that reach *F* > 1.1 are shown. The small symbols represent the individual datapoints. The surrounding color bands indicate the density of datapoints. The average energy cost for the configuration is given. Inset: schematic of considered configuration, where used electrodes are marked orange circles (inputs) and a green square (output, always at the bottom). **(c,d)** Same as **(a,b)** but for different input configuration. **(e–h)** Same as **(a–d)** but for the fully conductive comparison RNPU.
Figure 4. Functionality and power consumption comparison between capacitive and fully conductive RNPU for two input configurations. (a) Abundance of Boolean gates in Configuration 1 as a function of desired fitness in 10,000 randomly sampled control voltage combinations. Error bars represent 95% confidence values (Clopper and Pearson, 1934), representing the range where the true mean is likely to fall. (b) For each Boolean gate, energy costs for a single operation of all control voltage combinations that reach F > 1.1 are shown. The small symbols represent the individual datapoints. The surrounding color bands indicate the density of datapoints. The average energy cost for the configuration is given. Inset: schematic of considered configuration, where used electrodes are marked orange circles (inputs) and a green square (output, always at the bottom). (c,d) Same as (a,b) but for different input configuration. (e–h) Same as (a–d) but for the fully conductive comparison RNPU.

In Figure 4a, the abundance of Boolean gates is plotted as a function of minimum required fitness for Configuration 1, while Figure 4b shows the associated energy consumption per operation using the same set of random configurations. For this analysis a voltage combination was considered a proper gate if F > 1.1, as we found that the output reliably solves the target Boolean gate beyond this threshold. Energy per operation was estimated at the device level, explicitly excluding peripheral circuitry (e.g., digital-to-analog and analog-to-digital converters), using E = P · τ m . τ m is the minimum measurement time, derived from the theoretical operation speed (see Supplementary Material Note 1, Equations S1, S2), with the fit constant c from Equation 2 taken as the signal intensity i s. This definition provides a rigorous basis for comparison, as it jointly captures energy dissipation and intrinsic operational speed, thereby avoiding artificially favorable estimates for solutions that appear low-power but operate slowly due to low output currents. Although practical operation speeds may be affected by additional factors, the minimum measurement time in our estimate is set by the output signal magnitude through the signal-to-noise criterion. The found relative difference in energy per operation between the c-RNPU and the reference device therefore holds regardless of the absolute operation speed, making energy per operation a robust metric for comparison.

Configuration 1 shows a higher general density of logic gates and a more even distribution of them over corresponding energy consumption compared to the conductive input c-RNPU, Configuration 2 (Figures 4c,d). The abundance of Boolean gates for this mode is very similar to those reported by Chen et al. (2020). The results are shown in Figures 4e–h. The same configurations in terms of positions of input electrodes were used. This device was fabricated using the same fabrication procedure as the electrostatic device, so that the effect of the introduction of the capacitive electrodes on the power could be optimally dissected. This analysis was also repeated on the validation device, of which the results are shown in Supplementary Figure S4.

For both devices a higher density of Boolean gates was found for Configuration 1. This can be explained by the geometry of the device. In this configuration the inputs are furthest away from the output, while still being separated from each other. In previous works we have found that this provides maximum tunability in general (Ruiz Euler et al., 2020). Therefore, we attribute the higher density of Boolean gates in Configuration 1 primarily to this factor and conclude that capacitive electrodes can serve as inputs with similar efficacy to current-carrying electrodes.

We find that the average energy consumption per Boolean gate operation in the capacitive device is 0.13–0.19 µJ, more than an order of magnitude lower than 7–27 µJ found for the traditional device. Although the absolute energy-per-operation values depend on theoretical noise assumptions for an idealized system, the relative difference in efficiency between a conventional RNPU and a c-RNPU arises from their respective power consumption and output current levels. Additional noise sources present in practical implementations therefore do not affect this relative advantage. The difference in energy efficiency can be explained by noting that the introduction of capacitive electrodes does more than simply reduce the total current. The highest currents in traditional devices flow between nearest neighbors (Chen et al., 2020). These have been replaced by capacitive electrodes in c-RNPUs, effectively increasing the distance between current-carrying electrodes. Notably, both the average and the minimum energy per Boolean gate are reduced in c-RNPUs, evidencing a systematic improvement rather than a distributional shift.

The power consumption of the Boolean gates for the different configurations are separately depicted in Supplementary Figure S6. The average power consumption for the traditional device is very close to 1 μW, the value reported by Chen et al. (2020), even though those results were measured at 77 K. The average power consumption for the electrostatic device was found to be 0.12–0.15 µW, ∼10 times lower than that of the device with only current-carrying electrodes.

Hence, the introduction of capacitive electrodes reduces the energy per operation by approximately an order of magnitude, while retaining a similar abundance of Boolean gates. We attribute this improvement to two related effects. First, replacing half of the current-carrying electrodes strongly reduces the number of direct conductive pathways, since each conductive electrode can couple to several others. In a simple pairwise picture, this yields a reduction of roughly a factor of four in the total current. Second, the remaining conductive electrodes are spaced farther apart, suppressing the nearest-neighbor pathways that typically contribute most strongly to the current. Because transport in the RNPU is nonlinear, this increased spacing reduces current more strongly than expected from simple geometric scaling. Together, the reduced number of conductive pathways and the suppression of short-range conduction plausibly explain the observed order-of-magnitude reduction in energy per operation.

3.3 MNIST and FashionMNIST simulation

To benchmark the c-RNPU performance for a practical task, a circuit was trained in simulation to solve classification tasks, as explained below. The system was trained on the MNIST hand-written digit database (Deng, 2012) and the more challenging FashionMNIST database (Xiao et al., 2017).

In order to train a circuit of devices off-chip, we created a DNN surrogate model of the device using the method laid out by Ruiz Euler et al. (2020). To generate the training data, the output current of the device is recorded over a long time while sinewaves with various frequencies are applied to the inputs. The surrogate model consists of five hidden layers containing 90 nodes equipped with Silu activation functions. The model finally outputs all four currents. Figure 5a displays the model performance on predicting output currents on a test set of voltages, showing the model’s accuracy. The surrogate model achieves an RMSE of approximately 2.6 nA with a median stabilized percentage error of 2%, indicating strong absolute and relative accuracy, particularly at low currents.

Training of a network of electrostatic RNPUs to perform MNIST and FashionMNIST classification. **(a)** Predictions of RNPU surrogate model for test set of voltages compared to the measured current values. Inset: Distribution of corresponding errors. **(b)** Artificial neural network architecture that was used to perform classification of MNIST and FashionMNIST tasks using c-RNPUs. The (28 × 28) greyscale input image is fed into a linear layer with 30 outputs. These are fed in groups of three into the final layer containing 10 c-RNPUs. The ten outputs each correspond to one of the classes in the datasets. **(c)** Confusion matrix for MNIST classification. **(d)** Confusion matrix for FashionMNIST classification.
Figure 5. Training of a network of electrostatic RNPUs to perform MNIST and FashionMNIST classification. (a) Predictions of RNPU surrogate model for test set of voltages compared to the measured current values. Inset: Distribution of corresponding errors. (b) Artificial neural network architecture that was used to perform classification of MNIST and FashionMNIST tasks using c-RNPUs. The (28 × 28) greyscale input image is fed into a linear layer with 30 outputs. These are fed in groups of three into the final layer containing 10 c-RNPUs. The ten outputs each correspond to one of the classes in the datasets. (c) Confusion matrix for MNIST classification. (d) Confusion matrix for FashionMNIST classification.

The full artificial neural network (ANN) architecture is displayed in Figure 5b. The greyscale intensity of each pixel serves as input to a fully connected linear layer of size 784 × 30. The output of this layer is fed into a final stage comprising 10 c-RNPU models, each configured with three inputs and one output. Every c-RNPU receives as input a unique combination of three outputs from the linear layer. The three input electrodes are the current-carrying electrodes symmetrically positioned across the device. This configuration is displayed in Figure 5b. We chose this architecture as it has been proven to be an effective and straightforward method for MNIST classification by Ruiz Euler et al. (2021). The similarity in architectures means that the difference in results can be directly ascribed to the device itself, presenting a good opportunity to benchmark its potency in practical situations. Additionally, this architecture means that all control voltages are electrostatically applied, meaning all currents flow through the input and output electrodes.

We simulated the architecture for both the MNIST and FashionMNIST databases and for both a c-RNPU and an all current-carrying comparison device. Training of the architectures was performed using the Python Pytorch library. The linear layer is not biased and is manually clamped between minus one and one during the training phase, and sequentially multiplied by a factor to make sure that the outputs of the layer are not higher than the input values the RNPU model was trained on. The factors were chosen to be 0.08 for the electrostatic devices and 0.1 for the original RNPUs. The cross-entropy loss function was used as the criterion during training, which was carried out by a scheduled AdamW optimizer using a max learning rate of 0.02 and a linear anneal strategy. A weight decay of 1 · 10 − 5 was used in the optimizer. No systematic training parameter optimization was carried out.

The confusion matrices for both tasks are shown in Figures 5c,d. The overall accuracies and values for power consumption were summarized in Table 1. The reported numbers are the average over 10 trials, where the error represents the maximum observed deviation from this value. After 25 epochs the system reached 95.9% ± 0.2% accuracy on the test set, compared to 95% reported by Ruiz Euler et al. (2021) for the MNIST dataset. This is comparable to a multilayer perceptron classifier (MLPClassifier) with a hidden layer of 100 neurons or 2 hidden layers of 10 neurons, reported to be in the 92.1%–97.2% range (Xiao et al., 2017). The accuracy is closest to that of an MLPClassifier with 1 layer of 100 nodes with tanh activation function. Such a network uses more than 3 times the number of weights than our system. We find that the average power consumed per c-RNPU is ∼10 nW, while we find a range of 0.6–1 µW while using all current-carrying RNPUs. This means that using electrostatic RNPUs in this architecture preserves at least equal performance, while consuming 10x less power. For the FashionMNIST dataset we report an accuracy of 86.7% ± 0.2%. This is again comparable to MLPClassifier with a hidden layer of 100 neurons or 2 hidden layers of 10 neurons, reported to be in the 84.1%–87.1% range (Xiao et al., 2017). To obtain significantly higher classification accuracies, a convolutional neural network (CNN) should be utilized (Kadam et al., 2020).

TABLE 1. Results of training classification architecture for different cases. Test accuracies and power consumption for the four different cases that the artificial neural network was trained for. Power consumption is given per device, averaged across all simulated devices and operations.

DeviceTaskTest accuracy (%)Power consumption (µW)
c-RNPUMNIST95.9 ± 0.20.008 ± 0.002
FashionMNIST86.7 ± 0.20.018 ± 0.006
RNPUMNIST94.3 ± 0.40.87 ± 0.36
FashionMNIST85.9 ± 0.60.81 ± 0.38

For both MNIST and FashionMNIST, robustness was evaluated by comparing the surrogate model’s stabilized relative error to the relative separation between the top two predicted choices. The stabilized percent error quantifies prediction error relative to the signal magnitude with a small floor to avoid divergence at low values, while the stabilized percent margin measures the relative difference between the highest and second-highest predicted outputs. A conservative lower-bound margin was used: the 2nd percentile for MNIST (capturing 98% of samples) and the 5th percentile for FashionMNIST (capturing 95% of samples). For MNIST, the lower-bound margin is approximately 2.7%, while for FashionMNIST it is approximately 1.6%. Compared to a typical stabilized surrogate error of about 2%, this indicates that, in most cases, the separation between the top-ranked choices is on the same order as or larger than the surrogate uncertainty, supporting the robustness of the simulated outcomes.

An important question is how the improved power consumption translates into the system-level energy efficiency of RNPUs. Since energy efficiency is defined as the product of power consumption and measurement time, this consideration requires an estimate of the measurement time. We find a theoretical measurement time τ *m* = 2 ns (Supplementary Material: Note 1), but conservatively assume a practical limit τ *m* = 10 ns and use P = 10 nW. Zolfagharinejad (2026) showcases a computing architecture based on RNPUs using these numbers and arrive at a system-level energy efficiency of 15–30 TOPs/W, providing an example of how the energy efficiency gains found in this work open up practical energy-efficient applications of RNPUs. Benchmarking against the broader landscape of neuromorphic and in-memory computing hardware is complicated by the diversity of device concepts, computing paradigms, and measurement conditions across the field. This renders direct comparison of metrics such as TOPS/W difficult without careful qualification.

The 300 nm active region of the c-RNPU is compatible with an approximately 1 μm2 per-device footprint of integrated RNPU arrays (Escudero et al., 2026) and the order-of-magnitude reduction in core power consumption demonstrated here propagates directly into such system-level architectures.

4 Conclusion and outlook

To improve the energy efficiency of RNPUs, we incorporated capacitive electrodes into their design. These electrodes, separated from the active region by an ALD-grown AlOx layer, contribute non-trivially to the functionality of the device. The capacitive electrodes can be used solely as control electrodes in a configuration with conductive input electrodes but can also be used as input electrodes themselves. For both cases, all Boolean gates were successfully realized. Analysis of their abundance indicates a comparable capability to implement this functionality, while consuming more than 10 times less power than the predecessor device with all current-carrying electrodes. A network of these devices combined with a linear layer is able to solve MNIST and FashionMNIST with accuracies of 95.9% ± 0.2% and 86.7% ± 0.2%, respectively, with similar order of magnitude power reduction. The improvements in this work enables RNPU-based computing architectures with a system-level energy efficiency of 15–30 TOPs/W (Zolfagharinejad, 2026).

The advances presented in this work will become even more relevant the more the overhead in these devices is reduced. High-k dielectrics could replace AlOx to lower the required operating voltages, facilitating the integration of capacitive RNPUs into standard CMOS technology. In particular, we estimate that using 10 nm of hafnium oxide would reduce operating voltages sixfold, reducing operating voltages to below 1 V. Realizing this may require a more in-depth optimization of the fabrication process and analysis of reliability and leakage currents, which lie outside the scope of the present work.

Aging effects, hardware-in-the-loop training and inference, as well as integration of multiple devices into larger arrays, are natural next steps. Practical considerations including capacitive cross-talk between neighboring devices, signal integrity across layers, and mixed-signal peripheral integration remain open engineering questions for future work.

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Supplementary material

The Supplementary Material for this article can be found online at: https://www.frontiersin.org/articles/10.3389/fnano.2026.1823858/full#supplementary-material

Supplementary material Supplementary material at the source

Footnotes

Edited by: Tamalika Banerjee, University of Groningen, Netherlands

Reviewed by: Takahide Oya, Yokohama National University, Japan

Khoirom Johnson Singh, Dhanamanjuri University, India

Statements

Conflict of interest

The author(s) declared that this work was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.

The author WV declared that they were an editorial board member of Frontiers at the time of submission. This had no impact on the peer review process and the final decision.

Funding

The author(s) declared that financial support was received for this work and/or its publication. This study was funded by the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation) -SFB 1459/2 2025 -433682494. This project was funded by the European Union’s Horizon Europe research and innovation programme under Grant Agreement No 101046878. The funders played no role in study design, data collection, analysis and interpretation of data, or the writing of this manuscript.

Data availability

The raw data supporting the conclusions of this article will be made available by the authors, without undue reservation.

Author contributions

RC: Data curation, Visualization, Methodology, Validation, Formal Analysis, Conceptualization, Software, Investigation, Writing – review and editing, Writing – original draft. LK: Writing – review and editing, Writing – original draft, Methodology. WW: Supervision, Conceptualization, Funding acquisition, Writing – review and editing, Writing – original draft, Project administration.

Acknowledgements

We would like to thank Lorenzo Cassola for his contributions in the fabrication process and Mohamadreza Zolfagharinejad and Peter Bobbert for fruitful discussions. We thank Janiek van Slooten for helping obtain temperature-dependent data and Martin Siekman and Markus Schremb for technical support.

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Citation

Cool, R. J. C., et al. (2026). Tenfold power consumption reduction in reconfigurable nonlinear-processing units through capacitive control. Frontiers in Nanotechnology, Volume 8. https://doi.org/
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8 - 2026

Copyright

Copyright © 2026 Cool, Kingma and van der Wiel.

License: https://creativecommons.org/licenses/by/4.0/

*Correspondence: W. G. van der Wiel

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