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Frontiers in Nanotechnology ·

Volume 8 - 2026 | https://doi.org/10.3389/fnano.2026.1866642

Programming arbitrary analog conductance states of memristors in one step

  • Yongxiang Li1,2
  • Shiqing Wang1,2
  • Yubiao Luo1,2
  • Zhong Sun1,2,3*corresponding author
  1. 1Institute for Artificial Intelligence, Peking University, Beijing, China
  2. 2School of Integrated Circuits, Peking University, Beijing, China
  3. 3Beijing Advanced Innovation Center for Integrated Circuits, Beijing, China
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Abstract

The exponential growth of data-intensive workloads, spanning large-scale neural inference and scientific computing, has exposed the inherent bottlenecks of conventional von Neumann architecture. In-memory analog computing, which leverages memristive crossbar arrays, has emerged as a compelling alternative by enabling highly parallel matrix computations through the exploitation of fundamental physical laws. However, due to the intrinsic stochasticity of resistive switching dynamics, achieving high-precision analog programming becomes difficult and mandates iterative write-verify procedures. These digitally-controlled loops introduce substantial latency and peripheral hardware overhead, undermining the throughput and energy efficiency inherent to analog acceleration. We introduce a novel closed-loop feedback architecture that transforms analog-state programming into a self-regulated physical evolution. Unlike traditional discrete control loops, the proposed circuit utilizes its intrinsic dynamics to continuously sense the discrepancy between the instantaneous device conductance and a predefined target value. This error is converted in real time into a regulated feedback signal that drives the device toward the desired state, automatically halting the programming stimulus once the target is reached. Based on the fabricated memristor devices, experiment results show the circuit can achieve analog programming in one step (∼100 ns). Experimental results also validate successful 3-bit analog tuning within 100 ns, regardless of the initial conductance state. The average relative programming error is only about 2.2%. Moreover, a hybrid approach that augments this autonomous feedback with traditional write-verify cycles is adopted to enhance the programming precision. This approach improves overall programming speed by 3.7× compared to the traditional write-verify scheme. This work significantly improves the analog programming speed of memristor devices and offers a critical advancement for leveraging resistive memory in data-intensive storage-class applications and AI hardware.

Keywords

1 Introduction

The rapid proliferation of artificial intelligence (AI) and the Internet of Things (IoT) has driven an explosive increase in data requiring storage, transmission, and processing (Marengo, 2024; Huang et al., 2024; Baek et al., 2025). Under these circumstances, the conventional von Neumann architecture is proving inadequate due to the physical separation of memory and computation, which necessitates the continuous data movement between storage and processing units (Hennessy and Patterson, 2019; Sun et al., 2023). This bottleneck severely limits both system throughput and energy efficiency, particularly in data- and compute-intensive workloads, such as neural network inference, combinatorial optimization, and scientific computing (Sze et al., 2017; Ballard et al., 2014; Cai et al., 2020; Wan et al., 2022). To address these challenges, in-memory analog computing based on memristors, including resistive random-access memory (RRAM), phase-change memory (PCM), magnetic tunnel junction (MTJ) and ferroelectric tunnel junction (FTJ), has attracted widespread attention and is regarded as a highly promising computing paradigm (Ielmini and Wong, 2018; Joshi et al., 2020; Le Gallo et al., 2023; Zuo et al., 2025; Li et al., 2024a). In these systems, matrix elements are directly encoded as the conductance states of devices in crossbar arrays, enabling in situ matrix-vector multiplication (MVM) by exploiting Kirchhoff’s current law (KCL) and Ohm’s law (Sun and Huang, 2021). This mechanism facilitates highly parallel computation with physical O (1) complexity, thus significantly reducing both latency and energy consumption relative to conventional digital implementations. Furthermore, by combining this hardware with appropriate feedback circuits or iterative algorithms, its utility extends to more complex matrix equation tasks, including matrix inversion (INV) (Sun et al., 2019a) and matrix pseudo-inversion (PINV) (Mannocci et al., 2021; Wang et al., 2026). Such architectures also support high-level algorithmic applications, such as hyperdimensional computing (HDC) (Karunaratne et al., 2020) and compressive sensing (CS) (Wang et al., 2023). Overall, memristor-based in-memory analog computing offers a compelling route towards high-throughput, energy-efficient information processing for future intelligent systems (Sun et al., 2023).

However, the practical viability of these computing schemes relies fundamentally on the ability to precisely program individual device conductance to target analog values (Sebastian et al., 2020; Aguirre et al., 2024). This requirement remains challenging for memristors because their resistive-switching dynamics are governed by complex and highly nonlinear physical mechanisms, such as ion migration, filament formation, and thermal effects, all of which introduce intrinsic stochasticity into conductance evolution (Ielmini, 2016; Sun et al., 2019b; Wang et al., 2018). Therefore, the modulation of device conductance is often accompanied by pronounced cycle-to-cycle (C2C) and device-to-device (D2D) variations (Boybat et al., 2018; Mannocci et al., 2023; Li et al., 2024b), meaning that high-precision analog programming still relies predominantly on the write-verify strategy (Li et al., 2018; Yao et al., 2020). As shown in Figure 1A, each programming pulse is followed by a read-verification operation, and the next pulse is adjusted based on the measured conductance error. Although this algorithmic closed-loop approach can improve programming accuracy, reaching the target state within a prescribed tolerance typically requires tens of repeated cycles, resulting in substantial latency (Figure 1B). This limitation poses a significant challenge for applications that demand frequent state updates, such as storage-class memory (SCM), in situ neural network training, and edge inference systems (Freitas and Wilcke, 2008; Zhang et al., 2023; Lin et al., 2025). In addition, the write-verify strategy relies on extra peripheral circuits for data conversion (ADCs and DACs) and control modules, introducing further energy consumption, chip area overhead, and system-level design complexity (Yao et al., 2020; Rao et al., 2023). These non-negligible costs can substantially erode, and in some cases even negate, the intrinsic advantages of in-memory analog computing (Sun et al., 2023).

Illustration of the write-verify scheme. **(A)** Flowchart of the programming process. Following each programming pulse, a read operation is performed to determine whether the current conductance (*G*) falls within error tolerance (Tol) of the target conductance (*G* <sub>target</sub>). If this condition is not satisfied, a new cycle is initiated and the programming count (*N*) is incremented. The process continues until the target conductance is reached or the maximum allowed number (*N* <sub>max</sub>) is exceeded. **(B)** Conductance evolution during programming. Owing to the stochastic conductance change induced by each pulse, multiple programming iterations are generally required to reach *G* <sub>target</sub>.
Figure 1. Illustration of the write-verify scheme. (A) Flowchart of the programming process. Following each programming pulse, a read operation is performed to determine whether the current conductance (G) falls within error tolerance (Tol) of the target conductance (G target). If this condition is not satisfied, a new cycle is initiated and the programming count (N) is incremented. The process continues until the target conductance is reached or the maximum allowed number (N max) is exceeded. (B) Conductance evolution during programming. Owing to the stochastic conductance change induced by each pulse, multiple programming iterations are generally required to reach G target.

Against this backdrop, the self-terminating circuit has emerged as an important alternative strategy (Alayan et al., 2019; Levisse et al., 2020). Early designs were developed primarily for binary operations or logic devices (Lee et al., 2017). In these approaches, the switching event is detected through the transient current or voltage response of the cell, and the programming pulse is immediately interrupted, thereby reducing both programming energy and latency. Recently, this concept has been extended to multilevel and analog programming (Wang et al., 2022). By replacing repetitive write-verify loops with circuit-level feedback and automatic termination, these approaches enable the device conductance to evolve autonomously towards the target value within a single programming event, offering reduced programming latency and simplified peripheral circuitry. Nevertheless, the achievable accuracy of current self-terminating methods remains limited. Experimental demonstrations have been restricted to 1-bit programming (Yang et al., 2021; Chen et al., 2017; Chang et al., 2015; Xue et al., 2013), and simulation results have reached only 2-bit resolution (Wang et al., 2022). This precision remains insufficient for applications requiring high-density memory and in-memory analog computing (Xia and Yang, 2019; Song et al., 2024). Therefore, a programming method that is simultaneously fast and precise is lacking.

In this work, we propose a closed-loop circuit for programming arbitrary analog states into memristor devices. The circuit continuously senses the difference between the instantaneous device conductance and the target value through its intrinsic physical dynamics, converts this difference in real-time into a feedback programming signal, and thereby drives continuous conductance evolution. As the device state approaches the target value, the programming voltage is automatically suppressed, enabling self-termination of the programming process without iterative verification. We fabricated memristor devices and integrated them into the proposed framework to experimentally validate the circuit. The results demonstrate rapid programming within 100 ns, reliably tuning devices from arbitrary initial states to 3-bit target levels. Coupling this rapid autonomous coarse-tuning stage with the write-verify module for fine adjustment, we achieved high-precision programming (±3 μS) while substantially reducing both latency and energy overhead. These outcomes highlight the potential of the proposed method for rapid and low-energy analog programming.

2 Methods

Figure 2 illustrates the proposed high-speed self-terminating analog programming circuit. Consisting of only two operational amplifiers (OAs) and several fixed resistors with conductance G 0, the core architecture remains highly compact, thereby minimizing hardware overhead. One OA is configured as an analog inverter, the detailed structure of which is shown in the inset, while the other operates as a positive-feedback amplifier (PFA) to establish a global feedback loop across the circuit. Furthermore, a multiplexer (MUX) is employed to select among different reference resistors, where the conductance of the chosen resistor dictates the target state (G target) to which the memristor is programmed. Similarly, through MUX-based routing, the programming circuit can be interfaced with various memristor cells within the array, enabling efficient module reuse and facilitating scalable array-level operations. To mathematically model the operating principle of the circuit, we define the key node voltages labelled in Figure 2, where V in is the externally applied input voltage, and V out represents the output voltage of the PFA. When a memristor with an initial conductance G mem is connected to the circuit, its conductance state alters the instantaneous balance of the reference resistor branch. After being processed by the global feedback loop, this change is reflected in the programming voltage across the memristor (V 2−V 4), thereby establishing a dynamic coupling between the instantaneous conductance state and the applied voltage difference throughout the entire programming process. Specifically, the quantitative relationships among these variables can be derived on the basis of Ohm’s law and KCL as follows.

V in − V 1 G 0 = V 1 − V out G 0 + V 1 − V 3 G 0 + V 1 − V 2 G target (1)

V 2 − V 4 G mem = V 1 − V 2 G target (2)

V 1 − V 3 G 0 = V 3 − V 4 G 0 (3)

Circuit architecture of the high-speed self-terminating analog programming scheme, which composed of two OAs and several fixed resistors. The reference resistor defines the target conductance state, *G* <sub>target</sub>, whereas *G* <sub>mem</sub> denotes the memristor to be programmed, with both selected through the MUX.
Figure 2. Circuit architecture of the high-speed self-terminating analog programming scheme, which composed of two OAs and several fixed resistors. The reference resistor defines the target conductance state, G target, whereas G mem denotes the memristor to be programmed, with both selected through the MUX.

Equations 2, 3 are obtained by applying the virtual-short and virtual-open approximations to the positive and negative input terminals of the OA. Further accounting for the open-loop gain function in the complex frequency domain (s), the relationship between the input and output voltages is given by where L 0 denotes the DC gain, and ω 0 represents the 3-dB bandwidth of the OA. By combining Equations 1–5, the five variables, V 1−V 4 and V out, can be expressed in terms of the external parameters and circuit constants. After neglecting higher-order terms to simplify the analysis, the dynamic equations for nodes V 2 and V 4 across the memristor can be obtained as

V out = L s V 2 = ω 0 L 0 s + ω 0 V 2 , (4)

V 4 = − L s V 3 = − ω 0 L 0 s + ω 0 V 3 , (5)

5 + 5 c + 2 d V 2 / 4 s s 2 + c + 3 + 2 d L 0 ω 0 V 2 / 4 s s + 1 − c L 0 2 ω 0 2 V 2 / 4 s − 1 − c L 0 ω 0 2 V in s = 0 . (6)

Here, c is defined as G target/G mem, and d as G target/G 0. When c > 1, namely, the memristor conductance is lower than G target, the pole of the circuit resides in the right half of the complex plane, as shown in Figure 3. Correspondingly, the voltage at node V 2 is non-zero, indicating that the PFA is operating in the saturation region, with V out clamped to the OA supply voltage V DD. By substituting this result back into Equations 1–5, the effective programming voltage across the memristor is expressed as

V 2 − V 4 = 2 c 3 c + 3 + 2 d V DD + V in . (7)

Phase plane illustration of the programming circuit dynamics, which is governed by the ratio *c*. For *c* > 1, the system operates in the programming regime, driving the device conductance increases toward the target state. As the conductance approaches *G* <sub>target</sub> (*c* ≈ 1), the effective programming voltage vanishes, leading to automatic termination of the programming process. The stable state is likewise maintained when *c* < 1.
Figure 3. Phase plane illustration of the programming circuit dynamics, which is governed by the ratio c. For c > 1, the system operates in the programming regime, driving the device conductance increases toward the target state. As the conductance approaches G target (c ≈ 1), the effective programming voltage vanishes, leading to automatic termination of the programming process. The stable state is likewise maintained when c < 1.

When V in is adjusted such that Equation 7 yields a positive value, the circuit operates in the SET programming mode, driving the memristor conductance to increase toward G target. In particular, prior to connecting the memristor to the circuit, the equivalent conductance G mem can be approximated as zero. Accordingly, c tends to infinity, and the voltage difference simplifies to 2(V DD + V in)/3, independent of all other circuit parameters. This feature allows the initial programming voltage to be conveniently tuned by adjusting V in, enabling the proposed scheme to accommodate to various memristors with different material systems, device structures, and switching characteristics. Such flexibility highlights the versatility of the circuit and its considerable potential for broad practical applicability.

As the memristor conductance approaches G target, the corresponding value of c decreases continuously. When c = 1, the coefficients of the last two terms in Equation 6 become zero. In this regime, the contribution of the higher-order terms to the second-order frequency-domain equation is no longer negligible, and the governing dynamic equation of the circuit becomes Equation 8.

10 + 2 d V 2 / 4 s s 2 + 4 + 2 d L 0 ω 0 V 2 / 4 s s + 8 + d L 0 ω 0 2 V 2 / 4 s − 2 ω 0 2 V in = 0 (8)

The pole of the circuit also shown in Figure 3, and is located in the left half of the complex plane. Both OAs therefore operate in the linear region, yielding V 2 = V 4 = 0. At this stage, the dynamic coupling between the memristor conductance and the programming voltage is terminated, and the circuit settles into a stable equilibrium state. This result indicates that the circuit can autonomously determine when the target state has been reached and terminate the programming process without external intervention. The same behavior holds for c < 1, where the circuit remains stable and induces no further change in the device state.

The overall operating process of the programming system can thus be established as follows. Before being connected to the circuit, the memristor was first initialized to a low conductance state by a random RESET pulse, such that the starting point for subsequent programming satisfied the condition c > 1. Immediately after the device was connected, a programming voltage determined by V in was generated, continuously driving the conductance towards G target. During this process, the global feedback loop dynamically monitored the circuit state and modulated the effective programming conditions in response to the instantaneous conductance of the device. As the memristor conductance approached G target, strong dynamic feedback from OAs rapidly quenched the voltage across the device to zero. This feature enables self-termination during rapid programming, thereby suppressing severe overshoot without the need for additional verification or external control. This mechanism is particularly beneficial for memristor devices with strongly nonlinear current-voltage (I-V) characteristics. As the voltage difference across the device gradually decease, the effective conductance sensed by the circuit actually decreases in the low-voltage regime owing to their nonlinear characteristics. This prolongs the programming process, allowing for the continuous adjustment of the device state as it approaches the termination condition. This dual automatic compensation mechanism further mitigates the impact of over-programming. Overall, the proposed scheme forms a closed-loop analog programming framework that unifies state detection, dynamic regulation and self-termination within a single circuit, while ensuring stable operation throughout the entire programming process.

3 Results

3.1 Device fabrication, characterization and circuit validation

To experimentally verify the proposed programming circuit, we fabricated the memristor devices on a SiO2/Si substrate. First, a 5 nm Ti adhesion layer and a 40 nm Pt layer were patterned via photolithography and magnetron sputtering, followed by lift-off. Subsequently, a 5 nm HfO2 dielectric layer was formed by atomic layer deposition (ALD), as the resistive-switching layer. Finally, the top electrode consisting of 30 nm Ta and 40 nm Pt was deposited and patterned to complete the device structure. Figure 4A presents a cross-sectional transmission electron microscopy (TEM) image of the device, demonstrating distinct interfaces between the layers alongside key structural and material parameters. The basic electrical characteristics were measured using a Keysight B1500 A semiconductor parameter analyzer. As shown in Figure 4B, multi-level I-V sweeps obtained under externally controlled compliance current (I cc) confirm the analog programmability of the device. The results also indicate that the threshold voltage (V set) is below 1 V, providing a basis for the selection of V in. We then packaged several individual memristors (typically 8) into a 16-pin dual in-line (DIP-16) package and mounted them on a custom printed circuit board (PCB), which integrated the remaining circuit components. In the following experimental setup, the target resistor (G target) was implemented using discrete fixed resistors, the OAs were AD823A, and the multiplexers (MUX) were replaced by analog switches (74HC4052D).

Ta/HfO2-based memristor device. **(A)** TEM image of the device. **(B)** *I*-*V* characteristics of memristor devices. The device conductance is modulated via the compliance current (*I* <sub>CC</sub>), with 10 distinct *I* <sub>CC</sub> levels and 20 cycles for each.
Figure 4. Ta/HfO2-based memristor device. (A) TEM image of the device. (B) I-V characteristics of memristor devices. The device conductance is modulated via the compliance current (I CC), with 10 distinct I CC levels and 20 cycles for each.

Before validating the circuit’s stability through device programming, we first analyzed the voltages at the critical node across various c values to confirm that the circuit’s driving capability and dynamic response aligned with theoretical predictions. In the experiments, the supply voltage (V DD) was fixed at 2.4 V, and the feedback conductance of OAs (G 0) was set to 100 μS. Using 333 μS as the reference conductance, we replaced the memristor with a series of fixed resistor to record the corresponding voltage responses. The pulse voltages for controlling the switches were generated by a Tabor Electronics Model WW5064 four-channel waveform generator, and signal capture was performed with a RIGOL MSO8104 four-channel digital oscilloscope. The results are shown in Figure 5A, where the upper and lower waveforms correspond to V 2 and V 4, respectively. When t < 0, the device remains disconnected, and V in is set to −0.4 V, yielding an initial programming voltage of 1.33 V, consistent with the value calculated from Equation 7. When the conductance of the connected device is lower than G target (c > 1), a positive voltage drop is maintained across the device. Furthermore, a larger deviation of the device state from G target results in a proportionally greater voltage drop, as quantified in Figure 5B. Conversely, as c approaches 1, the voltage drop is rapidly suppressed, diminishing to zero once c ≤ 1. Furthermore, we experimentally evaluated the role of V in in regulating the initial programming voltage. As shown in Figure 5C, reducing V in from 0 V to −1 V decreased the initial voltage difference from 1.6 V to 0.93 V, in full agreement with the theoretical prediction of Equation 7. Based on the measured threshold characteristics of the fabricated device, V in was set to −0.4 V in the subsequent circuit experiments to provide sufficient programming capability. Collectively, these results confirm the soundness and feasibility of the proposed circuit design.

Programming-voltage response of the proposed circuit. **(A)** Transient waveforms of the node voltages *V* <sub>2</sub> (upper) and *V* <sub>4</sub> (lower) for different device conductance states at a fixed target conductance of 333 μS **(B)** Quantified relationship between the programming voltage, *V* <sub>2</sub>−*V* <sub>4</sub>, and the conductance mismatch ratio *c*. The voltage difference increases with increasing *c* in the *c* > 1 regime, and decreases rapidly to near zero as *c* approaches and falls below 1 **(C)** Dependence of the initial programming voltage on the differential input bias *V* <sub>in</sub>.
Figure 5. Programming-voltage response of the proposed circuit. (A) Transient waveforms of the node voltages V 2 (upper) and V 4 (lower) for different device conductance states at a fixed target conductance of 333 μS (B) Quantified relationship between the programming voltage, V 2−V 4, and the conductance mismatch ratio c. The voltage difference increases with increasing c in the c > 1 regime, and decreases rapidly to near zero as c approaches and falls below 1 (C) Dependence of the initial programming voltage on the differential input bias V in.

3.2 Fast self-terminating multi-level programming

After verifying the basic characteristics of the circuit, we conducted experiments on memristor devices. The target conductance was again set to 333 μS (3 kΩ), and a 10 μs programming pulse was applied in the first experiment to capture the complete programming dynamics. Figure 6 shows a representative case where the initial device conductance was randomly RESET to 59.9 μS. At the beginning, the circuit provided a voltage difference of 1.33 V, exceeding the threshold voltage of the memristor. Thus, upon connection to the circuit, the device conductance increased immediately, leading to pronounced changes in the voltages at nodes V 2 and V 4. The final conductance reached 327 μS, corresponding to a deviation of only 1.8% from G target.

Illustration of the one-step analog conductance programming experiment. The left and right panels show the pre-read and post-read results of programming, respectively, and the middle panel shows the transient responses of the node voltages *V* <sub>2</sub> and *V* <sub>4</sub>. For *G* <sub>target</sub> = 333 μS and a 10 μs pulse, the device conductance was tuned from 59.9 μS to 327 μS, with a programming error of 1.8%.
Figure 6. Illustration of the one-step analog conductance programming experiment. The left and right panels show the pre-read and post-read results of programming, respectively, and the middle panel shows the transient responses of the node voltages V 2 and V 4. For G target = 333 μS and a 10 μs pulse, the device conductance was tuned from 59.9 μS to 327 μS, with a programming error of 1.8%.

It should be noted that the voltage waveform remained almost stable throughout the pulse, especially V 2 dropped close to zero. Although the voltage difference did not vanish completely due to parasitic parameters in the PCB circuit, it fell below the threshold voltage required to induce any further change in the state of our devices, indicating that the actual conductance update was concentrated within a much shorter interval at the onset of the pulse. For bulk-switching devices (Diao et al., 2025), whose conductance continuously responds to voltages with varying amplitudes, this persistent low-voltage feedback near the termination condition could introduce a more severe risk of conductance offset (G mem > G target). To address this issue, in addition to suppressing circuit non-idealities through a fully integrated implementation, the overshoot can also be mitigated by shortening the programming time. In this case, the device response can still be approximated as quasi-linear, while the proposed circuit maintains real-time feedback between the device conductance and the programming voltage.

To evaluate the speed limit of this scheme, we systematically carried out experiments using pulse widths of 5 μs, 1 μs, 300 ns, and 100 ns, targeting the same conductance state of 333 μS (Figure 7). As the pulse width decreased, the final conductance in all cases reached G target within an error of about 7%, supporting our interpretation that the initial unstable portion of the waveform captures the actual programming event. This observation is also consistent with the intrinsic fast-switching behavior of memristors, which arises from the abrupt nature of the SET process (Waser and Aono, 2007; Wong et al., 2012). These results indicate that the proposed closed-loop feedback mechanism supports not only self-termination, but also an exceptionally fast dynamic response on sub-microsecond timescales.

Transient waveforms of the programming process at different programming pulse widths, where **(A)** 5 μs, **(B)** 1 μs , **(C)** 300 ns and **(D)** 100 ns.
Figure 7. Transient waveforms of the programming process at different programming pulse widths, where (A) 5 μs, (B) 1 μs , (C) 300 ns and (D) 100 ns.

Under 100 ns pulse conditions, we further programmed the devices to predefined 3-bit target conductance levels and performed a statistical analysis of the programming performance. As shown in Figure 8A, the initial states were all generated by applying random RESET pulses, resulting in an approximately uniform conductance distribution in the range of 10–260 µS. This ensures that the evaluation faithfully reflects the reliability of the proposed scheme under diverse initial state conditions. The 3-bit target conductance levels were defined as [50, 66.7, 100, 137, 170, 213, 256, 333] µS, respectively, and 40 independent programming trials were carried out for each state to ensure statistical significance. Figure 8B quantifies the final distribution at each target level in the form of cumulative distribution function (CDF). The clear separation among these curves indicates that the programmed states are well resolved and remain highly distinguishable. Specifically, the maximum programming error is 9.1%, with an average error of 2.2%. Taken together, these results confirm the repeatability and stability of the proposed write circuit for rapid multi-level programming.

Statistical characteristics of multilevel analog conductance programming in the proposed circuit. **(A)** Statistical results of one-step programming to 3-bit conductance levels from arbitrary initial states. Different colors denote the *G* <sub>target</sub> of 50, 66.7, 100, 137, 170, 213, 256 and 333 μS, respectively, with 40 cycles for each level. **(B)** CDF of the final programmed conductance levels, demonstrating clear separation between the individual states.
Figure 8. Statistical characteristics of multilevel analog conductance programming in the proposed circuit. (A) Statistical results of one-step programming to 3-bit conductance levels from arbitrary initial states. Different colors denote the G target of 50, 66.7, 100, 137, 170, 213, 256 and 333 μS, respectively, with 40 cycles for each level. (B) CDF of the final programmed conductance levels, demonstrating clear separation between the individual states.

3.3 Hybrid programming with write-verify scheme

Considering that conductance variations across individual devices in an array can accumulate and propagate into output errors (Li et al., 2025), the proposed scheme is particularly suitable for inherently robust applications such as HDC, in which moderate programming inaccuracies can be tolerated without degrading overall performance (Ge and Parhi, 2020; Kent et al., 2020). In such contexts, programming speed and efficiency are often of greater practical importance than achieving extremely control over the final conductance state. By contrast, precision-sensitive applications, including scientific computing and signal processing (Zidan et al., 2018; Lu et al., 2014), impose far more stringent requirements on programming accuracy and device-state uniformity. Consequently, the proposed scheme alone is insufficient to satisfy the accuracy demands of these tasks.

To overcome this limitation, we integrated the proposed scheme with the write-verify strategy. The one-step programming circuit first rapidly brings the device conductance close to G target, after which the write-verify circuit is employed as a back-end fine-tuning module to further narrow the distribution of the coarsely programmed results. This hybrid scheme substantially reduces both the programming voltage and the number of cycles required to achieve the same tolerance, thus providing a more favorable trade-off among programming precision, latency and energy overhead than the write-verify-only approach. As illustrated in Figure 9, the one-step self-terminating scheme can be used directly in applications with an error tolerance of 5%–10%, whereas for more stringent scenarios, the write-verify module can be enabled to further tighten the device state distribution within a narrower window, for example, ±3–5 μS, with only a limited number of fine-tuning cycles.

Comparison of the one-step programming scheme and the hybrid programming scheme. **(A)** Schematic illustration of one-step programming, in which the device is driven directly to the vicinity of the target conductance, with a programming precision of approximately ±8%. **(B)** Schematic illustration of hybrid programming, in which a back-end write-verify module is introduced to further suppress programming variation, achieving a precision of ±3 μS (≈1%) within only a few cycles.
Figure 9. Comparison of the one-step programming scheme and the hybrid programming scheme. (A) Schematic illustration of one-step programming, in which the device is driven directly to the vicinity of the target conductance, with a programming precision of approximately ±8%. (B) Schematic illustration of hybrid programming, in which a back-end write-verify module is introduced to further suppress programming variation, achieving a precision of ±3 μS (≈1%) within only a few cycles.

Building on the previously demonstrated one-step 3-bit programming results, we further carried out fine-tuning experiments with a ±3 μS tolerance window. The write-verify module is fully automated through Python scripts that control a microcontroller unit (MCU). The MCU is integrated on the PCB and interfaces with DACs to apply precise voltage pulses to the memristor, while ADCs are used to monitor its current state. Figure 10A shows the results from 150 experimental trials for each target conductance level. The state distributions become more tightly confined, while the margins between adjacent states are substantially increased, enabling the accuracy required for high-precision in-memory analog computing. Meanwhile, the programming overhead is markedly reduced. As shown in Figure 10B, all target states are achieved in fewer than 12 cycles (with the average of 7.9 cycles), corresponding to a 3.7× reduction compared with the write-verify-only scheme. This benefit is especially pronounced for high-conductance states. For instance, the imposed error window for the 333 μS state corresponds to a tolerance of nearly 1%, a condition that remains challenging for conventional write-verify programming and requires 75 cycles in our experiments. Even under this stringent condition, the proposed hybrid scheme still achieves rapid programming, delivering a 6.6× speed improvement. Finally, we summarized all experimental results in Table 1, including the 3-bit target conductance values, initial-state range, final-state averages and distributions, deviations from the target states, and the required number of programming cycles for both the one-step programming scheme and the hybrid programming scheme with write-verify.

High-precision programming results enabled by the hybrid scheme. **(A)** 3-bit level distributions after fine-tuning following one-step programming, showing a final programming precision of approximately ±3 μS. **(B)** Comparison of the cycles required to achieve the final precision in the write-verify-only and hybrid schemes, with the hybrid scheme delivering an overall acceleration of 3.7×.
Figure 10. High-precision programming results enabled by the hybrid scheme. (A) 3-bit level distributions after fine-tuning following one-step programming, showing a final programming precision of approximately ±3 μS. (B) Comparison of the cycles required to achieve the final precision in the write-verify-only and hybrid schemes, with the hybrid scheme delivering an overall acceleration of 3.7×.

TABLE 1. Comparison of the one-step programming scheme and the hybrid programming scheme with write-verify.

One-step programming scheme
Target levelInitial state rangeFinal state averageFinal state rangeDeviation
Hybrid-programming with write-verify
Target levelFinal state averageFinal state rangeDeviationProgramming cycles
5018.6-38.249.745.5-53.82.4
66.718.2-51.065.961.5-71.23.1
10019.6-75.299.392.9-107.74.3
13717.5-92.0137.0126.7-147.46.3
17025.7-122.5169.6156.9-183.28.2
21324.8-163.0212.5196.8-229.99.9
25627.7-192.5249.4235.9-275.69.3
33320.3-110.9332.6306.4-353.015.1
5050.147.1-53.01.71.8
66.766.863.8-69.71.87.6
10099.997.0-103.01.96.0
137137.0134.0-140.01.87.9
170169.7167.1-172.91.79.5
213213.2210.1-216.01.711.0
256256.2253.2-259.01.78.2
333332.8330.0-336.01.811.4

4 Conclusion

In conclusions, by replacing iterative write-verify control with a continuously regulated feedback mechanism rooted in the intrinsic circuit physics, the proposed framework transforms analog-state programming from a digitally controlled, cycle-by-cycle adjustment process into a self-regulated analog evolution towards the target level. Experimental validation using fabricated memristor devices demonstrates successful tuning from arbitrary initial states to 3-bit target levels under 100 ns programming pulses, highlighting the feasibility of high-speed multi-level programming. When further combined with a write-verify module for fine tuning, the resulting hybrid scheme achieves high-precision programming with only a few additional cycles, providing a 3.7× improvement over the write-verify-only approach. These results together represent a substantial step towards ultra-fast, low-power analog-state programming and provide a promising pathway for the deployment of resistive memory technologies in SCM and AI hardware accelerators.

Generative AI statement

The author(s) declared that generative AI was not used in the creation of this manuscript.

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Footnotes

Edited by: Andrea Padovani, University of Modena and Reggio Emilia, Italy

Reviewed by: Zhuo Diao, Osaka University, Japan

K. Rajalakshmi, PSG College of Technology, India

Statements

Conflict of interest

The author(s) declared that this work was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.

Funding

The author(s) declared that financial support was received for this work and/or its publication. This research was supported by the National Natural Science Foundation of China (Grant No. 62572011), the Beijing Natural Science Foundation (Grant No. 4252016), and the 111 Project (Grant No. B18001).

Data availability

The original contributions presented in the study are included in the article/supplementary material, further inquiries can be directed to the corresponding author.

Author contributions

YoL: Writing – original draft, Writing – review and editing, Data curation, Formal Analysis, Investigation, Software, Validation, Visualization. SW: Writing – original draft, Conceptualization, Data curation, Formal Analysis, Investigation, Methodology, Validation, Visualization. YuL: Writing – original draft, Data curation, Investigation, Software, Validation. ZS: Writing – original draft, Writing – review and editing, Conceptualization, Funding acquisition, Methodology, Project administration, Resources, Supervision.

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Citation

Li, Y., et al. (2026). Programming arbitrary analog conductance states of memristors in one step. Frontiers in Nanotechnology, Volume 8. https://doi.org/
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8 - 2026

Copyright

Copyright © 2026 Li, Wang, Luo and Sun.

License: https://creativecommons.org/licenses/by/4.0/

*Correspondence: Zhong Sun

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