Implementation and performance evaluation of CMOS-integrated memristor-driven flip-flop circuits

1 Introduction

The rapid global adoption of artificial intelligence (AI) and machine learning (ML) has placed unprecedented demands on modern computing hardware. Conventional complementary-metal-oxide-semiconductor (CMOS)-based digital systems, despite decades of scaling and optimization, face fundamental limitations when applied to AI workloads that require massive parallelism, high memory bandwidth, and energy-efficient data movement (Shooshtari et al., 2025).

The von Neumann bottleneck, stemming from the physical separation of computation and memory, results in significant overhead due to constant data shuttling between memory and processing units (Shooshtari et al., 2025; Mohith and Sakthivel, 2026). As AI models grow in size and complexity, this bottleneck increasingly dominates power consumption and latency, creating a critical need for alternative hardware paradigms capable of supporting compute-in-memory and low-energy operations (Roy et al., 2025).

Memristors have emerged as one of the most promising post-CMOS nanodevices for overcoming these bottlenecks (Aguirre et al., 1974). As the fourth fundamental passive circuit element, a memristor exhibits a unique relationship between charge and magnetic flux, giving it the ability to “remember” its resistance state even in the absence of applied power, thereby demonstrating its non-volatile property. The memristor intrinsically combines nonvolatile memory and analog/digital computation within the same nanoscale device. This nonvolatile resistive switching originates from ionic drift, filament formation, or oxygen vacancy migration in nanoscale materials, phenomena that scale favourably with device dimensions. Unlike CMOS transistors, whose leakage currents increase significantly with scaling, memristors exhibit ultra-low leakage and are capable of multi-state storage. Their nanoscale footprint enables extremely high device densities, and their compatibility with back-end-of-line (BEOL) fabrication allows stacking above CMOS layers, leading to true 3D integration. Its ability to store state as resistance, retain information without continuous power, and perform logic operations directly through resistive switching presents a powerful departure from CMOS-only logic implementations.

Despite extensive work on memristor-based combinational logic, including NAND, NOR, XOR, and implication-style logic families, relatively limited research has been conducted on its application to sequential logic elements, which are fundamental for registers, counters, memory buffers, and finite-state machines used in AI datapaths and control units (Hur et al., 2017; Vourkas and Sirakoulis, 2016; Dai et al., 2023; Wang et al., 2022; Rasheed S and Nelapati, 2024). Demonstrating reliable memristor-driven flip-flops and storage elements is therefore crucial for enabling full-stack memristive digital systems. The non-volatile nature of memristor-driven flip-flops could enable instant-on digital systems, reduce checkpointing overhead, and significantly improve power-down power-up resilience for embedded and edge-AI platforms.

Early studies established the feasibility of integrating logic and storage using stacked memristor-CMOS structures, enabling state-retentive logic primitives that form the foundation of non-volatile sequential circuits (Dai et al., 2023; Wang et al., 2022; Rasheed S and Nelapati, 2024; Rziga et al., 2022; Dhongade and Singh, 2022; Yan et al., 2022; Cho et al., 2016). Subsequent works demonstrated that memristor-inspired and memristor-based combinational logic circuits can achieve substantial reductions in power and area compared to CMOS technologies, while also addressing variability concerns through optimized device characteristics (Dhongade and Singh, 2022; Yan et al., 2022). Building on these advances, several researchers proposed non-volatile latch designs, including optimized pure-memristor latches and hybrid memristor–CMOS D latches, which exhibit lower static power, reduced device count, and improved energy efficiency, making them suitable for low-power sequential applications (Rasheed S and Nelapati, 2024; Rziga et al., 2022; Dhongade and Singh, 2022). More recent designs further enhanced latch performance by focusing on area efficiency, energy–delay trade-offs, and detailed comparative analysis with CMOS counterparts (Rziga et al., 2022). At the flip-flop level, innovative architectures such as D and JK flip-flops demonstrated compact implementation and flexible timing behavior (Dai et al., 2023; Wang et al., 2022; Rasheed S and Nelapati, 2024; Rziga et al., 2022; Dhongade and Singh, 2022; Yan et al., 2022; Cho et al., 2016). Additionally, ReRAM-based non-volatile latches have been shown to provide strong radiation hardness, extending the applicability of memristive sequential elements to space and safety-critical environments (Yan et al., 2022). Overall, the literature indicates that memristor-based latches and flip-flops offer significant advantages in power, area, non-volatility, and functionality, although challenges related to variability, endurance, and large-scale integration remain active research topics (Aguirre et al., 1974; Hur et al., 2017; Vourkas and Sirakoulis, 2016; Dai et al., 2023; Wang et al., 2022; Rasheed S and Nelapati, 2024; Rziga et al., 2022; Dhongade and Singh, 2022; Yan et al., 2022; Cho et al., 2016).

On the other hand, previously we explored various memristor-inspired combination logics (Nawaria et al., 2023; Ghodke et al., 2023), including half/full adder, half/full subtractor, decoder, encoder, multiplexer, and various fundamental logic gates by using experimentally pre-validated memristor framework (Kumar et al., 2021), which showed remarkable performance improvements as compared to the existing CMOS technology and other reported memristor-based state-of-the-art work. Therefore, by considering the aforementioned needs, herein, we extend the memristor logic paradigm by designing and analyzing a complete set of both logic gates and sequential digital circuits using a hybrid memristor-CMOS approach. Building upon the memristive device characteristics and logic methodology established in our previous study, we introduce efficient designs for inverter, NAND, NOR, and XOR gates, and also further develop memristor-driven implementations of essential sequential elements, including D, T, JK, and SR flip-flops. Here, it should be noted that the utilized memristor framework was thoroughly experimentally validated with the experimental data of Y₂O₃-based memristive devices as reported in our previous work (Kumar et al., 2021). These circuits are evaluated for functional correctness, switching behavior, and potential advantages in area efficiency and power reduction. By combining non-volatile resistive memory with CMOS signal restoration, the proposed architectures offer a practical pathway toward low-power, high-density digital subsystems suitable for integration into future AI computing platforms. This expanded design space, encompassing both combinational and sequential logic, lays the groundwork for developing full-scale memristor-augmented digital processors and neuromorphic systems. The insights gained here contribute to the broader effort of bridging memory and computation, reducing idle power, and enabling the ultra-efficient hardware required for the continued advancement of AI technologies.

This article is organized as follows. Section 2 introduces the experimentally validated memristor framework and the physical interpretation of the utilized parameters in modelling. Section 3 describes the design methodology and implementation of memristor-driven combinational logic gates and sequential circuits (flip-flop). This section also describes the various performance metrics, such as area, power, and delay, and their comparison with other state-of-the-art work with existing 90 nm CMOS technology. Section 4 summarizes the conclusion and future scope of the research work.

2 Memristor framework

Here in, a detailed explanation and parameter interpretation were provided for the utilized memristor framework (Kumar et al., 2021), which was dually pre-validated with the experimental data of Y₂O₃ and WO₃-based memristive devices (Kumar et al., 2021) (see Supplementary Figure S1 in supporting information). Equation 1 describes the current-voltage (I-V) relation of the utilized memristor framework, wherein several constants were utilized. Table 1 shows the parameter values and physical interpretation of these parameters as used in Equations 1–3.

I t = b 1 w a 1 e α 1 V i t ‐ 1 + χ e γ V i t ‐ 1 , V i t ⩾ 0 b 2 w a 2 e α 2 V i t ‐ 1 + χ e γ V i t ‐ 1 , V i t < 0 (1)

TABLE 1. Physical interpretation and numerical values of parameters used in modeling.

The first term on the right side of Equation 1 shows flux-controlled memristive behaviour, and the second term denotes the ideal diode behaviour in I-V characteristics. Herein, V _i(t) is the applied input voltage.

Equation 2 represents the piecewise window function, f(w), which ensures that the state variable (w) is varied between 0 and 1. Additionally, the range of parameter p defines the boundary of the window function (f(w)) between 0 and 1, and if p is greater than 10, the upper value of f(w) is more than 1, which does not follow the essential conditions for the window function, as reported by Prodromakis et al. (2011).

f w = log 1 + w p , 0 ≤ w ≤ 0.1 1.1 p , 0.1 < w ≤ 0.9 2 − w p , 0.9 < w ≤ 1 (2)

The time derivative of the state variable, w(t), is shown by Equation 3, which also depends on the nature of the input voltage and window function.

d ω d t = A × v i m t × f w (3)

Equation 3 consists of two constants, A and m, and these are the two independent variables that affect the time derivative of the state variable. Therefore, to ensure that the opposite polarity of the applied voltage results in the opposite change in the rate of change of the state variable, parameter m must always be an odd number. Additionally, the previously described models (Prodromakis et al., 2011; Yakopcic et al., 2011) are associated with bipolar memristive systems, while the utilized memristor framework was well-suited for both unipolar and bipolar memristive systems, which further increases the flexibility of the memristor framework.

3 Circuit design methodology and results and discussion

3.1 Circuit design methodology: logic gates

3.1.1 Inverter

The memristor-based inverter is the fundamental building block for all other gates. The proposed design utilizes a hybrid CMOS-memristor architecture as shown in Figure 1a, consisting of a single memristor and one NMOS transistor. For the inverter shown in Figure 1a, one terminal of the memristor is connected to V D D, when V I N = 1 (high input voltage), the NMOS transistor turns “ON”, and the memristor is in the “SET” condition (high resistance). While the NMOS is in the saturation mode, wherein the “ON” resistance is nearly equal to 0. Hence, the output becomes 0. On the other hand, when V I N = 0 (low input voltage), the transistor switches into the “cutoff” region; however, the memristor holds the previous resistance value (high), and hence, V O U T is nearly equal to “1,” followed by some voltage drop across the memristor.

3.1.1.1 OR/AND gate

To implement an OR gate, two memristors are connected in parallel as shown in Figure 1c. Here, one terminal of the memristor is connected to input A and B, while the other terminal of both memristors is connected to the common node output. If both inputs are the same, (0,0) or (1,1), both memristors become identical, and hence, there will be no voltage drop between terminals A and B, so the output follows the input 0 and 1, respectively. For the asymmetric input combination, there will be a current flow from one terminal to another based on the input combination. For A = 1 and B = 0/A = 0 and B = 1, the current will flow from A→B/B→A, which impacts the memristor’s states. Here, the memristor connected to input 1 offers low resistance, and the other offers high resistance, allowing current to flow from A→B/B→A. The voltage drops across the memristor in the low state, resulting in an output voltage of 1. For symmetric input pairs, the output matches the input, while for asymmetric inputs, the output is 1. Figure 1d demonstrates the simulation waveforms for OR logic. A memristor-based AND gate circuit is shown in Figure 1e, in which memristors are inverted, resulting in the memristor states being opposite. For symmetric inputs, the output matches the input. For asymmetric inputs, consider the (1,0) case. Now M1 offers high resistance, and M2 offers low resistance. The voltage drops across M2, resulting in 0 V at the output node. Hence, for asymmetric inputs, the output is 0. This behaviour is clearly demonstrated in the results shown in Figure 1f.

3.1.1.2 NAND and NOR gate

The NAND and NOR gates are the universal gates from which all other logic functions can be designed. The NAND and NOR gates are designed using three memristors and one PMOS/NMOS transistor, as compared to the conventional design, where two NMOS and two PMOS transistors are used. The NAND gate is implemented using a memristor-based AND gate followed by a memristor-based inverter, as shown in Figure 1g. Inputs A and B each drive a memristor (horizontal devices); their right terminals are shorted to form a common internal node. This internal node controls the gate of the NMOS transistor; the NMOS source is at GND, and the drain goes to the output Y. A vertical memristor from Y to ground provides a conditional pull-down path whose resistance depends on the previous programming/current state, assisting discharge when both inputs activate the network. Similarly, the NOR gate is implemented using an OR gate followed by an inverter, as shown in Figure 1i. Figures 1h,j show the simulation waveform for the NAND and NOR gates, respectively.

3.1.1.3 XOR gate

The XOR gate can be implemented using the combination of AND OR logic as A ⊕ B = A + B . A . B ¯. The circuit implementation of the same is shown in Figure 1k. For the input combinations 00, 01, 10, the AND gate produces output 0, which turns “OFF” the NMOS transistor; hence, the output node follows OR logic. While for input 11, the AND gate output becomes 1, which turns “ON” the NMOS transistor, and the output node gets connected to ground, producing output 0. The proposed design reduces the number of components as compared to the traditional CMOS design, which requires 8–12 transistors. The simulation waveform for the XOR gate is shown in Figure 1l. The same XOR logic is used in the next section to implement the flip-flops.

3.2 Circuits design methodology: sequential logic circuits

In this section, D, T, JK, and SR flip-flops are designed using a hybrid memristor-CMOS approach to exploit the advantages of both emerging and conventional technologies. The proposed designs integrate memristors with CMOS logic to achieve reduced transistor count, lower power consumption, and improved area efficiency compared to conventional CMOS-only implementations. Memristors are utilized for their nonvolatile memory characteristics and compact structure, enabling efficient logic realization, while CMOS transistors provide signal restoration and reliable switching performance. The hybrid architecture ensures correct logical functionality of all flip-flop configurations while maintaining compatibility with standard CMOS fabrication processes. Simulation results demonstrate that the proposed hybrid memristor-CMOS flip-flops exhibit improved power–delay characteristics, making them suitable for low-power and high-density sequential circuit applications.

3.2.1 D flip-flop

The operation of the proposed D flip-flop (Q n + 1 = D) is based on a controller (or master)-responder configuration formed by cascading two D latches as shown in Figure 2a. The first latch (controller latch) is negative-level triggered, while the second latch (responder latch) is positive-level triggered. Memristors are employed only in the realization of inverter stages within the latches, whereas the remaining circuitry is implemented using a CMOS transistor negative-level-triggered latch. While the second latch (responder latch) is positive-level-triggered, the controller latch is active and samples the input data D, while the responder latch remains isolated, holding its previous state. As the clock transitions from low to high, the controller latch is disabled, thereby locking the sampled data, and simultaneously, the responder latch becomes active, transferring the stored value to the output.

During the high level of the clock, changes at the input do not affect the output due to the inactive controller latch. Consequently, the overall configuration exhibits positive edge-triggered behaviour, with the output updating only at the rising edge of the clock signal, ensuring stable and reliable data storage.

3.2.2 T flip-flop

The T flip-flop can be realized using the D flip-flop by incorporating additional combinational logic at the input. For the implementation of the T flip-flop shown in Figure 3, the D input of the flip-flop is driven by the XOR function of the T input and the present output Q, such that D = T ⊕ Q = T Q ¯ + T ¯ Q. When T input is low, the XOR output remains equal to the current state of Q, causing the D flip-flop to retain its previous state at the next active clock edge. Conversely, when the T input is high, the XOR output becomes the Q ¯, forcing the D flip-flop to toggle its state on the rising edge of the clock. Since the underlying D flip-flop operates in a positive-edge-triggered manner, the T flip-flop also updates its output only at the clock’s rising edge. This approach ensures correct toggle functionality while benefiting from the low-power and area-efficient characteristics of the hybrid memristor-CMOS D flip-flop design.

3.2.3 SR flip-flop

The SR flip-flop is implemented using the proposed D flip-flop by appropriately defining the logic at the D input to realize set and reset operations. In the design shown in Figure 4, the D input is expressed as D = S + R ¯ Q where S and R denote the set and reset inputs, respectively, and Q represents the present state of the flip-flop. When the set input S is asserted, the D input is forced high, and the flip-flop sets its output Q = 1 s e t at the rising edge of the clock. When the reset input R is asserted, the term R ¯ becomes low, forcing the D = 0 and resetting the output Q = 0 r e s e t at the next clock edge. If both S = R = 0, the D input follows the present state Q h o l d, thereby holding the previous output. The underlying positive-edge-triggered D flip-flop ensures that all state transitions occur synchronously with the clock. The invalid condition of S = R = 1 is avoided in this implementation to prevent undefined behaviour, resulting in a reliable and clocked SR flip-flop suitable for sequential circuit applications.

3.2.4 JK flip-flop

The JK flip-flop is implemented using the proposed D flip-flop by realizing appropriate combinational logic at the D input to achieve the required switching behavior as shown in Figure 5. In this configuration, the D input is defined as D = J Q ¯ + K Q. When J = K = 0 , the D input follows the current value of Q h o l d, and the flip-flop holds its previous state at the next rising clock edge. When J = 1 , K = 0, the first term dominates, forcing the D input high and setting Q = 1 s e t the output. Conversely, when J = 0 , K = 1, the second term becomes inactive, driving the D input low and resetting Q = 0 r e s e t the output. When both J = K = 1, the D input becomes Q ¯ t o g g l e, causing the flip-flop to toggle its state. Since the core D flip-flop operates in a positive edge–triggered manner, all state transitions of the JK flip-flop occur synchronously at the rising edge of the clock, eliminating race conditions and ensuring stable operation within the hybrid memristor–CMOS framework.

3.3 Results and discussion

In this section, we thoroughly evaluated and discussed the performance of the proposed memristor-based various sequential circuits using SPECTRE and compared them with the previously reported state-of-the-art memristor-based circuit designs as well as CMOS-based circuit designs. Herein, Table 2 represents a comparative analysis of the proposed D latch with previously implemented and reported data (Nawaria et al., 2023; Roy et al., 2025) and a conventional CMOS-based design (Yan et al., 2022). The comparison was carried out in terms of total component count used in the specific circuit design, average power consumption, and delay. In terms of transistor usage, the proposed design utilizes 6 transistors, which is comparable to existing designs and lower than that reported in (Rziga et al., 2022; Yan et al., 2022). The CMOS design relies entirely on transistors (8 transistors) and does not use memristors, highlighting the advantage of hybrid memristor-CMOS architectures in reducing active device count.

TABLE 2. Performance evaluation and comparison of the D latch with other state-of-the-art work.

Scaled for 90 nm technology node for fair comparison.

A significant improvement was observed in the average power consumption. The proposed design exhibits the lowest power consumption of 7.1 µW, which was substantially lower than the other reported state-of-the-art-work (Vourkas and Sirakoulis, 2016; Rasheed S and Nelapati, 2024; Rziga et al., 2022; Dhongade and Singh, 2022; Yan et al., 2022). Compared to Rasheed et al (Rasheed S and Nelapati, 2024), Rziga et al (Rziga et al., 2022), and Yan et al (Dhongade and Singh, 2022), the power reduction was approximately 66%, 74%, and 76%, respectively. Additionally, as compared with the CMOS-based logic implementation (Vourkas and Sirakoulis, 2016), the proposed design demonstrates a power reduction of more than 50%. This significant reduction can be attributed to the use of memristors, which offer non-volatile behavior and reduced switching activity, thereby minimizing dynamic power dissipation. The outcomes clearly indicate that the proposed design was well-suited for low-power and energy-efficient memory and computing applications. The propagation delay of the proposed circuit was measured at 219 ps, which was higher than some aggressively optimized designs (Vourkas and Sirakoulis, 2016; Rasheed S and Nelapati, 2024) that report delays in the order of a few picoseconds. However, the majority of previous data have not reported delay values, which limits direct comparison. Moreover, as compared with the CMOS implementation, which exhibits a delay of 10,000 ps, the proposed design achieves an improvement of nearly two orders of magnitude. Although the delay is not the minimum among all designs, it represents a reasonable trade-off considering the substantial gains in power efficiency and reduced reliance on purely transistor-based logic. Additionally, a first-order technology scaling approach was adopted, where delay was assumed to scale linearly with feature size, while power was assumed to scale with the 1.5^th power of the feature size, and detailed analysis was presented in supporting information.

Table 3 represents the performance evaluation of the proposed memristor-based D flip-flop and its comparison with the previously reported designs (Dai et al., 2023; Wang et al., 2022; Rasheed S and Nelapati, 2024; Cho et al., 2016). A significant improvement was observed in average power consumption, as compared with other reported data, and the proposed design consumed only 14.2 µW. As observed, the proposed D flip-flop design was more power-efficient than designs reported by Dai et al (Dai et al., 2023), Rasheed et al (Rasheed S and Nelapati, 2024), and Cho et al (Cho et al., 2016), and showed power reduction of more than 60% (Dai et al., 2023; Rasheed S and Nelapati, 2024) and about 39% (Cho et al., 2016), respectively. Additionally, the propagation delay of the proposed D flip-flop was 209.5 ps, showing a clear improvement as compared to other reported literature (Aguirre et al., 1974). However, in our case, the propagation delay was slightly higher than reported by Cho et al (Cho et al., 2016). Overall, the outcomes demonstrate that the proposed design achieves an effective trade-off between low power consumption and delay.

TABLE 3. Performance evaluation and comparison of the D flip-flop with other state-of-the-art work.

Scaled for 90 nm technology node for fair comparison.

Similarly, Table 4 represents the performance evaluation of the proposed memristor-based JK flip-flop and its comparison with previous state-of-the-art work (Wang et al., 2022; Cho et al., 2016). It should be noted that the proposed JK flip-flop achieves a significant reduction in average power consumption, dissipating only 14.2 µW, which was substantially lower than that reported by Wang et al. (2022) and Cho et al. (2016), and it was overall improved by approximately 74% (Dhongade and Singh, 2022) and 90% (Cho et al., 2016), respectively. This highlights the effectiveness of memristor integration in minimizing power dissipation. Moreover, the propagation delay of the proposed design was 147 ps, which was significantly lower than previously reported data (Cho et al., 2016). On the other hand, we thoroughly examined all the performance parameters for both T and SR, as discussed in Table 5, but we were unable to compare their performance with any existing memristor-based circuits due to the non-availability of suitable literature. Therefore, the presented work can add significant advantages to the literature and pave a new path in designing fast and power-efficient sequential circuits for memory and computation applications. Furthermore, Figure 6 shows the average delay, power, and power-delay-product (PDP) for all the proposed memristor-based sequential circuits. Additionally, the utilized delay formulation is given in supporting information (see Supplementary Figure S2).

TABLE 4. Performance evaluation and comparison of the JK flip-flop with other state-of-the-art work.

Scaled for 90 nm technology node for fair comparison.

TABLE 5. Performance evaluation parameters of proposed memristor-based sequential circuits in this work.

Scaled for 90 nm technology node for fair comparison.

Supplementary Figures S3, S5 in supporting information show the transient response analysis of the logic circuits which were used to design and implement various FF circuits. These analyses include corner analysis (see Supplementary Figure S3), temperature variation (see Supplementary Figure S4), and voltage variation (see Supplementary Figure S5). Supplementary Figure S6 shows the voltage transfer characteristics of a single unity-gain transition along with a detailed discussion on the set-up time, hold time, and noise margin.

Additionally, energy-delay product (EDP) was calculated for the designed circuits and presented in Supplementary Table S1 in supporting information.

4 Conclusion

In summary, we investigated CMOS-integrated memristor-driven logic gates and sequential logic circuits (flip-flop), which were designed and implemented in the industry-standard Cadence Virtuoso. The utilized memristor framework was experimentally pre-validated and showed low variance, as confirmed by in-house fabricated memristive devices. Moreover, the proposed memristor-driven logic circuits were integrated with 90 nm CMOS technology, which showed significant improvement in performance in terms of the usage of the number of components, total circuit area, and utilized power as compared to the other state-of-the-art work reported in the literature. Overall, various performance metrics such as area, power, and delay of these sequential circuits were found to be reduced by more than ∼24%, 60%, and 58%, respectively. Therefore, the designed sequential circuits are highly reliable for their use in future complex circuits and integrated circuits (ICs). Additionally, this work further opens the possibility to design and implement power, area, and delay-efficient circuits for the registers, counters, amplifier, oscillator, and neural networks.

Generative AI statement

The author(s) declared that generative AI was not used in the creation of this manuscript.

Any alternative text (alt text) provided alongside figures in this article has been generated by Frontiers with the support of artificial intelligence and reasonable efforts have been made to ensure accuracy, including review by the authors wherever possible. If you identify any issues, please contact us.

Publisher’s note

All claims expressed in this article are solely those of the authors and do not necessarily represent those of their affiliated organizations, or those of the publisher, the editors and the reviewers. Any product that may be evaluated in this article, or claim that may be made by its manufacturer, is not guaranteed or endorsed by the publisher.

Supplementary material

The Supplementary Material for this article can be found online at: https://www.frontiersin.org/articles/10.3389/fnano.2026.1890628/full#supplementary-material

Supplementary material Supplementary material at the source

Footnotes

Edited by: Sajid Husain, University of California, Berkeley, United States

Reviewed by: Ziang Chen, Friedrich Schiller University Jena, Germany

Manoj Kumar, Netaji Subhas University of Technology, India