Eliminating vendor lock-in in quantum machine learning via framework-agnostic neural networks

1 Introduction

The past decade has witnessed a rapid expansion in both the theoretical foundations and practical implementations of quantum machine learning (QML). Variational quantum algorithms (VQAs) (Cerezo et al., 2021; Peruzzo et al., 2014) have emerged as the dominant paradigm for exploiting noisy intermediate-scale quantum (NISQ) devices (Preskill, 2018), with parameterized quantum circuits (PQCs) serving as the central computational primitive (Benedetti et al., 2019). These circuits interleave parameterized unitary gates with entangling operations, forming quantum analogues of classical neural network layers. When coupled with classical optimizers through hybrid quantum-classical loops, PQCs have demonstrated promising results in classification (Havlíček et al., 2019; Schuld et al., 2020), representation learning (Liu et al., 2022), and reinforcement learning (Yen-Chi Chen et al., 2020; Owen and Si, 2020).

Despite this progress, the software ecosystem for QML remains deeply fragmented. TensorFlow Quantum (TFQ) (Broughton et al., 2020) provides tight integration with the TensorFlow computational graph and the Cirq circuit library (Developers, 2023), but offers no native support for PyTorch-based workflows or non-Google hardware. PennyLane (Bergholm et al., 2022) introduced a plugin architecture that supports multiple backends, yet its automatic differentiation engine is tightly coupled to its own device abstraction, making it difficult to export circuits to non-PennyLane ecosystems without manual translation. Qiskit Machine Learning (Qiskit, 2023) is optimized for IBM Quantum hardware (Contributors, 2023) but provides limited interoperability with competing cloud platforms such as Amazon Braket (Amazon Web Services, 2023) or Azure Quantum (Microsoft, 2023). This fragmentation creates a phenomenon that is well understood in classical cloud computing but has received insufficient attention in the quantum domain: vendor lock-in.

Vendor lock-in in QML manifests along three axes. First, at the framework level, a model trained using TFQ tensors cannot be directly fine-tuned using PyTorch autograd, because the parameter representations, gradient tape mechanisms, and loss function interfaces are incompatible. Second, at the hardware level, a circuit designed for IBM superconducting qubits may require non-trivial transpilation to execute on IonQ trapped-ion hardware (IonQ Inc., 2023) or Rigetti quantum processors (Rigetti Computing, 2023), and the necessary transpilation passes are not shared across frameworks. Third, at the encoding level, different frameworks implement data encoding strategies with subtly different gate decompositions, making it impossible to guarantee that the same classical input vector produces identical quantum states across platforms.

The consequences of this lock-in are severe. Researchers cannot reproduce results obtained with a competing framework without re-implementing the entire model. Institutions that invest heavily in one ecosystem face prohibitive migration costs when that vendor deprecates features, raises prices, or discontinues hardware. Of particular concern, the inability to compare models across frameworks on identical hardware undermines the scientific validity of benchmark comparisons, because observed performance differences may reflect framework overhead rather than algorithmic merit.

In this paper, we address all three axes of vendor lock-in through a unified framework-agnostic quantum neural network (QNN) architecture. Our contributions are as follows. First, we present a multi-framework integration layer that exposes a single QNN definition to TensorFlow, PyTorch, and JAX simultaneously, with automatic translation of parameter tensors, gradient computations, and loss functions. Second, we introduce a hardware abstraction layer (HAL) that provides a uniform API for circuit submission, result retrieval, and transpilation across IBM Quantum, Amazon Braket, Azure Quantum, IonQ, and Rigetti backends. Third, we define three pluggable data encoding strategies, namely, amplitude encoding, angle encoding, and instantaneous quantum polynomial (IQP) encoding, with numerically verified equivalence across all supported backends. Fourth, we develop a multi-framework export pipeline that uses Open Neural Network Exchange (ONNX) (ONNX Consortium, 2023) metadata to translate trained QNN circuits to Qiskit, Cirq, PennyLane, and Braket representations without loss of parameter fidelity. Fifth, we provide comprehensive benchmarks on three classification tasks and hardware validation on IBM Heron r2 processors (up to 156 qubits), demonstrating that our abstraction layers introduce minimal overhead while enabling extensive cross-platform portability.

The remainder of this paper is organized as follows. Section 2 surveys existing QML frameworks and their interoperability limitations. Section 3 describes the multi-framework architecture. Section 4 presents the hardware abstraction layer. Section 5 formalizes the data encoding strategies. Section 6 details the export pipeline and ONNX integration. Section 7 reports benchmark results. Section 8 presents hardware validation experiments. Section 9 discusses the implications and limitations of our findings. Section 10 concludes the paper and discusses future directions.

2 Related work

2.1 Quantum machine learning frameworks

TensorFlow Quantum (TFQ) (Broughton et al., 2020) was among the first frameworks to integrate quantum circuit simulation within a mature classical deep learning ecosystem. TFQ represents quantum circuits as Cirq (Developers, 2023) objects that are embedded within TensorFlow computational graphs, enabling end-to-end automatic differentiation of hybrid quantum-classical models. The primary advantages of TFQ include its native support for batched circuit execution, its compatibility with the extensive TensorFlow ecosystem (including Keras, TensorBoard, and TFLite), and its ability to use TensorFlow’s distributed computing infrastructure for parallelized circuit simulations. However, TFQ is fundamentally limited to the Cirq circuit representation and to Google-supported backends, preventing deployment on IBM, IonQ, or Rigetti hardware without manual circuit translation.

PennyLane (Bergholm et al., 2022) adopted a different design philosophy, introducing a plugin-based device system in which quantum circuits are written in a framework-agnostic syntax and then dispatched to backend-specific simulators or hardware. PennyLane supports automatic differentiation through the parameter-shift rule (Schuld et al., 2019), finite differences, and adjoint methods, and provides interfaces to PyTorch, TensorFlow, and JAX. Despite this breadth, PennyLane’s interoperability is achieved through its own intermediate representation rather than through native integration with each classical framework’s autograd engine. Consequently, complex hybrid architectures that require deep integration with, for example, PyTorch’s dynamic computational graph or JAX’s just-in-time (JIT) compilation pipeline may experience performance degradation or feature limitations when mediated through PennyLane’s abstraction layer.

Qiskit Machine Learning (Qiskit, 2023) is a component of the broader Qiskit ecosystem (Contributors, 2023) developed by IBM. It provides high-level constructs for quantum kernel methods (Havlíček et al., 2019), quantum neural networks, and variational classifiers. Qiskit Machine Learning benefits from tight integration with IBM Quantum hardware and the Qiskit Runtime service, which enables session-based execution with reduced latency. However, its dependence on the Qiskit circuit model means that migrating a trained model to a competing platform requires re-expressing the circuit in an entirely different gate set and parameter convention.

2.2 Parameterized quantum circuits and variational algorithms

The theoretical foundations of variational quantum algorithms have been extensively studied in the context of NISQ-era computing (Preskill, 2018; Bharti et al., 2022). The variational quantum eigensolver (VQE) (Peruzzo et al., 2014; Kandala et al., 2017; Liu et al., 2019) and the quantum approximate optimization algorithm (QAOA) (Farhi et al., 2014) established the hybrid quantum-classical optimization paradigm. Mitarai et al. (Mitarai et al., 2018) introduced the concept of quantum circuit learning, demonstrating that PQCs can serve as universal function approximators when the circuit depth and entanglement structure are chosen appropriately. Schuld and Killoran (Schuld and Killoran, 2019) formalized quantum models as kernel methods operating in feature Hilbert spaces, a perspective that has influenced much subsequent work on quantum advantage in machine learning (Liu et al., 2021; Huang et al., 2021; Kübler et al., 2021). Recent experimental work has demonstrated quantum advantage in learning from experiments (Huang et al., 2022), although dequantization results (Tang, 2022) caution that apparent quantum speedups may not always survive classical algorithmic improvements.

The expressibility and trainability of PQCs have been characterized by several important results. Sim et al. (Sim et al., 2019) proposed quantitative measures of expressibility and entangling capability, providing tools for comparing circuit ansatze, and Du et al. (Du et al., 2020) further analysed the expressive power of parameterized circuits as function approximators. McClean et al. (McClean et al., 2018) identified barren plateaus in the training landscapes of deep random quantum circuits, a finding that has significant implications for circuit architecture design. Arrasmith et al. (Arrasmith et al., 2021) showed that barren plateaus affect gradient-free optimization methods as well, limiting the utility of evolutionary or Nelder–Mead approaches as workarounds. Subsequent work has explored conditions under which barren plateaus can be avoided, including quantum convolutional architectures (Cong et al., 2019; Arthur et al., 2021), hierarchical classifiers (Grant et al., 2018), and Hamiltonian variational ansatze (Wiersema et al., 2020). Sharma et al. (Sharma et al., 2022) extended trainability analysis to dissipative perceptron-based QNNs, and Beer et al. (Beer et al., 2020) demonstrated strategies for training deep quantum neural networks. The role of noise in exacerbating trainability challenges has also been characterized (Wang et al., 2021). Generalization bounds for QML models have been established by Caro et al. (Caro et al., 2022), and Hubregtsen et al. (Hubregtsen et al., 2022) investigated practical training of quantum embedding kernels on near-term hardware. Tensor network methods offer an alternative route to scalable quantum-inspired machine learning (Huggins et al., 2019).

2.3 Hardware platforms and cloud access

The quantum hardware landscape is characterized by competing technological approaches. IBM Quantum provides cloud access to superconducting transmon processors, with Eagle-class devices such as IBM Brisbane offering 127 qubits (Kim et al., 2023) and the newer Heron r2 generation reaching 156 qubits. Google’s Sycamore processor (Arute et al., 2019) demonstrated quantum supremacy on a sampling task, and subsequent work has explored utility-scale quantum computation on Eagle-class processors. IonQ (IonQ Inc., 2023) offers trapped-ion quantum computers with all-to-all connectivity, which can simplify circuit compilation for certain algorithms. Rigetti Computing (Rigetti Computing, 2023) provides superconducting processors with a distinctive chip architecture, and Amazon Braket (Amazon Web Services, 2023) serves as a multi-provider gateway offering access to IonQ, Rigetti, and Oxford Quantum Circuits (OQC) hardware through a unified API.

Despite the existence of multi-provider access points such as Amazon Braket and Azure Quantum (Microsoft, 2023), these platforms do not solve the framework-level lock-in problem. A circuit developed using PennyLane cannot be executed through the Qiskit Runtime without manual translation, and a model trained using TFQ’s gradient tape cannot resume training using PyTorch’s autograd. Our work addresses this gap by providing a framework-agnostic intermediate representation that sits above the hardware access layer.

2.4 Interoperability and standardization Efforts

The Open Neural Network Exchange (ONNX) (ONNX Consortium, 2023) standard has been successful in enabling interoperability among classical deep learning frameworks, allowing models trained in PyTorch to be deployed on TensorFlow Serving and vice versa. However, ONNX does not currently define operators for quantum gates or parameterized quantum circuits. Peres and Galvão (Peres and Galvão, 2023) explored Pauli-based compilation as a route to hardware-agnostic circuit representations, but their work focused on circuit optimization rather than framework interoperability. To our knowledge, no prior work has proposed a comprehensive solution that addresses framework-level, hardware-level, and encoding-level lock-in simultaneously.

3 Multi-framework architecture

3.1 Design principles

Our architecture is guided by three design principles: (i) a QNN model should be defined once and be executable from any supported classical framework without modification; (ii) the gradient computation mechanism should respect the native autograd capabilities of the host framework; and (iii) the overhead introduced by the abstraction layer should be negligible relative to the quantum circuit execution time.

The core abstraction is the QuantumLayer, a framework-agnostic object that encapsulates a parameterized quantum circuit, its encoding strategy, and a measurement specification. The QuantumLayer maintains an internal representation of the circuit as a directed acyclic graph (DAG) of gate operations, where each gate is characterized by its type (from a universal gate set { R x , R y , R z , CNOT , CZ , H , S , T }), its qubit targets, and its parameter binding. This internal DAG is independent of any vendor-specific circuit representation.

3.2 Framework adapters

To integrate with each classical framework, we define a set of framework adapters that translate between the QuantumLayer’s internal representation and the host framework’s tensor operations. Specifically, we implement three adapters: TFAdapter (targeting TensorFlow (Abadi et al., 2016)), TorchAdapter (targeting PyTorch (Paszke et al., 2019)), and JAXAdapter (targeting JAX (Bradbury et al., 2018)). Each adapter performs three functions.

First, the adapter wraps the QuantumLayer as a differentiable operation in the host framework’s computational graph. Each adapter registers the quantum circuit evaluation as a custom differentiable operation using the host framework’s extension mechanism for user-defined layers, ensuring that gradients computed by the quantum layer are directly propagated into the host framework’s automatic differentiation engine.

Second, the adapter manages parameter synchronization. When the host framework’s optimizer updates the classical parameters, the adapter propagates these updates to the QuantumLayer’s internal parameter store. Conversely, when the quantum circuit execution returns measurement outcomes, the adapter converts these into the host framework’s native tensor format.

Third, the adapter handles batched execution. Classical deep learning frameworks expect operations to be vectorized over a batch dimension. Our adapters support batched circuit execution by either parallelizing independent circuit evaluations (on hardware) or by leveraging the simulator’s native batching capabilities (as provided by, e.g., TFQ’s tfq.layers.Expectation).

The overall architecture is depicted in Figure 1.

3.3 Unified parameter representation

A critical challenge in multi-framework integration is ensuring that parameter representations are consistent across frameworks. TensorFlow uses tf.Variable objects with eager or graph-mode semantics; PyTorch uses torch.nn.Parameter tensors with automatic gradient tracking; JAX uses immutable pytree structures. To reconcile these differences, our QuantumLayer maintains parameters as NumPy arrays in a canonical format and provides bidirectional conversion functions for each framework.

Formally, let θ ∈ R p denote the vector of p trainable circuit parameters. The canonical representation stores θ in a framework-independent numerical format. Each framework adapter maintains bidirectional conversion functions ϕ F and ϕ F − 1 that map between this canonical store and the host framework’s native parameter type, minimizing memory copies where the underlying runtime permits.

3.4 Gradient computation

Gradient computation in hybrid quantum-classical models requires special treatment because the quantum circuit is not directly differentiable through classical backpropagation. The standard approach is the parameter-shift rule (Schuld et al., 2019; Mari et al., 2021), which computes exact gradients of expectation values by evaluating the circuit at shifted parameter values.

For a parameterized gate U ( θ j ) = e − i θ j G / 2, where G is a Hermitian generator with eigenvalues ± 1, the parameter-shift rule gives:where f ( θ j ± π / 2 ) denotes the expectation value evaluated with θ j shifted by ± π / 2. Our framework implements this rule at the QuantumLayer level, following the methodology of Mitarai and Fujii (Mitarai and Fujii, 2019), independent of the host framework’s autograd engine. The framework adapter then injects the resulting gradient tensor into the host framework’s backward pass.

∂ ∂ θ j ⟨ ψ θ | O ̂ | ψ θ ⟩ = 1 2 f θ j + π 2 − f θ j − π 2 , (1)

This design allows the user to select the gradient strategy at instantiation time, choosing between the exact parameter-shift rule, finite differences (for gates with non-standard generators), or the adjoint method (for simulator-only execution). The gradient computation mechanism is summarized in Algorithm 1.

Algorithm 1. Framework-Agnostic Gradient Computation.

4 Hardware abstraction layer

4.1 Motivation

Quantum hardware platforms differ along multiple dimensions: gate sets, qubit connectivity, gate fidelities, measurement protocols, job submission APIs, and result formats. A circuit designed for a heavy-hex lattice topology (IBM) cannot be directly executed on an all-to-all connected trapped-ion processor (IonQ) without re-routing, and vice versa. The hardware abstraction layer (HAL) mediates these differences by providing a uniform interface for circuit submission, transpilation, execution, and result retrieval.

4.2 Architectural design

The HAL is organized as a layered architecture comprising a backend discovery and capability registry, a modular transpilation pipeline that converts vendor-independent circuits into backend-native instructions, and an execution management layer that provides unified job submission, retrieval, and session management across all supported cloud providers. The Execution Manager supports both synchronous (blocking) and asynchronous (callback-based) execution modes.

The transpilation pipeline converts an abstract vendor-independent circuit C abs into a backend-native circuit C native through a sequence of compiler passes tailored to the target backend’s gate set and connectivity. The correctness criterion requires that C native and C abs produce the same unitary (up to a global phase) on all valid input states, as expressed in Equation 2:

U C native = e i ϕ U C abs , ϕ ∈ 0,2 π . (2)

4.3 Supported backends

Table 1 summarizes the quantum backends currently supported by our HAL, along with their key characteristics. Figure 2 provides a visual representation of the compatibility between our framework and each hardware platform.

TABLE 1. Supported quantum hardware backends and their characteristics. Devices and qubit counts are representative of the platforms integrated during development. The hardware experiments in Section 8 additionally use IBM Heron r2 (ibm_fez, 156 qubits), IQM Garnet, and IonQ Forte-1.

4.4 Backend selection and routing

When a user does not specify a target backend, the HAL provides an automatic backend selection mechanism that optimizes for a user-specified objective. Let B = { B 1 , B 2 , … , B m } represent the set of available backends. For each backend B k, the HAL computes a composite suitability score s k (Equation 3) based on the circuit characteristics and the backend’s calibration data:where fidelity ( B k , C ) estimates the expected circuit fidelity based on the average gate error rate and the circuit depth, connectivity ( B k , C ) measures the degree to which the circuit’s qubit interactions match the backend’s coupling map, and queue_time ( B k ) is the estimated wait time in the provider’s job queue. The weights α, β, γ are user-configurable.

s k = α ⋅ fidelity B k , C + β ⋅ connectivity B k , C − γ ⋅ queue_time B k , (3)

4.5 Authentication and credential management

The HAL manages authentication credentials for multiple cloud providers through a unified credential store. Credentials are stored in an encrypted local vault (AES-256) and are injected into provider-specific SDK calls at execution time. The credential store supports IBM Quantum API tokens, AWS IAM credentials (access key and secret key), Azure service principal authentication, IonQ API keys, and Rigetti QCS access tokens. This approach ensures that the user need only configure credentials once, regardless of how many frameworks or backends are used in a given experiment.

5 Data encoding strategies

5.1 Overview

The choice of data encoding, which maps classical input data into quantum states, is a critical design decision that affects both the representational capacity and the trainability of a QNN (Schuld and Petruccione, 2018; LaRose and Coyle, 2020). Our framework provides three pluggable encoding strategies: amplitude encoding, angle encoding, and instantaneous quantum polynomial (IQP) encoding. Each strategy is implemented as a subclass of the abstract Encoder class and is compatible with all supported backends through the HAL.

5.2 Amplitude encoding

Amplitude encoding represents a classical vector x ∈ R N (with N = 2 n for n qubits) directly as the amplitudes of a quantum state, as given in Equation 4:where | i 〉 denotes the i-th computational basis state. This encoding achieves logarithmic compression, encoding an N-dimensional vector into log 2 N qubits. However, the state preparation circuit requires O ( N ) gates in the general case (Schuld and Petruccione, 2018), which can negate the qubit efficiency advantage for NISQ devices with limited coherence times.

Our implementation uses a recursive decomposition based on uniformly controlled rotations. The classical vector x is first normalized, and then a sequence of multiplexed R y rotations is applied to construct the target state. The circuit depth scales as O ( 2 n ) in the worst case, but the implementation includes an approximation parameter ϵ that truncates small-amplitude components, reducing the depth to O ( 2 n ( 1 − ϵ ) ) at the cost of a bounded approximation error (Equation 5):

‖ | ψ amp 〉 − | ψ ̃ amp 〉 ‖ 2 ≤ ϵ . (5)

5.3 Angle encoding

Angle encoding maps each classical feature x j to a rotation angle on a dedicated qubit, as shown in Equation 6:

This encoding requires n qubits for n features (one qubit per feature) and uses a circuit of depth one, making it highly suitable for NISQ devices. The disadvantage is that the encoding does not introduce entanglement, so any entanglement in the model must come from subsequent variational layers.

Our implementation supports three rotation axes (R x, R y, R z) and a combined encoding that uses two rotations per qubit, effectively doubling the encoding density (Equation 7):

5.4 IQP encoding

Instantaneous quantum polynomial (IQP) encoding (Havlíček et al., 2019; Schuld and Killoran, 2019) introduces feature-dependent entanglement through a circuit consisting of Hadamard gates, diagonal phase gates, and controlled-Z (CZ) operations, as defined in Equation 8:where U_IQP is given by Equation 9,and S is a set of qubit pairs defining the entanglement structure. The IQP encoding can be repeated r times (data re-uploading) to increase the feature map’s expressibility (Goto et al., 2021), although Thanasilp et al. (2022) have shown that deep quantum kernel circuits can suffer from exponential concentration, which must be considered when selecting the number of repetitions. The number of repetitions r and the entanglement set S are configurable parameters.

U IQP x = ∏ j , k ∈ S CZ j k ⋅ e i x j x k Z j Z k ⨂ j = 1 n H ⋅ e i x j Z j , (9)

The encoding strategies are compared in Table 2, and representative circuit diagrams are shown in Figure 3.

TABLE 2. Comparison of data encoding strategies. N denotes the classical input dimension, n the number of qubits.

5.5 Encoding equivalence across backends

A key requirement of our framework is that the same classical input produces an identical quantum state regardless of which backend executes the circuit. This is non-trivial because different backends may decompose high-level gates differently. To ensure equivalence, we verify at transpilation time that the decomposed circuit implements the same unitary as the abstract encoding circuit. Formally, for each encoding strategy E and each backend B k, we verify:where ‖ ⋅ ‖ F denotes the Frobenius norm, U E , B k is the unitary implemented by the transpiled circuit on backend B k, U E , ref is the reference unitary from the abstract encoding, and δ is a tight numerical tolerance. This verification is performed using statevector simulation at circuit compilation time.

U E , B k x − U E , ref x F < δ , (10)

6 Multi-framework export and ONNX

6.1 Export pipeline design

A trained QNN model encapsulates three components: the circuit structure (gate types and qubit layout), the trained parameters ( θ * ), and the encoding configuration. To enable model portability, our framework provides export functions that translate the internal representation into the native circuit format of each supported target framework.

Each export function translates gates, binds trained parameters, converts measurement specifications, and serializes model metadata into the target format. Where a direct gate mapping does not exist between the internal representation and the target library, the export function applies the minimal decomposition automatically.

The export pipeline is illustrated in Figure 4.

6.2 ONNX integration

The Open Neural Network Exchange (ONNX) (ONNX Consortium, 2023) provides a standardized format for representing machine learning models as computational graphs. While ONNX does not natively support quantum operations, we extend its schema with a custom domain that introduces operator types for quantum circuit representation, data encoding configuration, and measurement specification. These custom operators allow the full hybrid model (including both classical and quantum layers) to be serialized, version-controlled, and deployed within a single ONNX model file without loss of information.

6.3 Round-trip fidelity

To verify that the export-import pipeline preserves model fidelity, we define a round-trip test. For each pair of supported frameworks ( F i , F j ), we train a QNN model in framework F i on the Iris dataset for 100 epochs, export the model using the appropriate to_X() function, import the model into framework F j and evaluate on the test set, and compare the predicted probability vectors element-wise.

Let p i and p j denote the output probability vectors from frameworks F i and F j respectively for a given test input. The round-trip fidelity is defined in Equation 11 as:

F RT = 1 − 1 | D test | ∑ x ∈ D test ‖ p i x − p j x ‖ 1 . (11)

As summarized in Table 3, the round-trip fidelity exceeds 0.9999 for all framework pairs when using the simulator backend, confirming that the export pipeline introduces negligible numerical error. The small residual ( < 1 0 − 4 ) is attributable to floating-point differences between NumPy, TensorFlow, and PyTorch linear algebra backends.

TABLE 3. Round-trip fidelity F RT for all framework export pairs, evaluated on the Iris test set (30 samples, simulator backend).

7 Benchmarks

7.1 Experimental setup

We evaluate our framework on three standard classification tasks that have been widely used in the QML literature (Schuld et al., 2020; Havlíček et al., 2019; Abbas et al., 2021). The first task is Iris (Schuld and Petruccione, 2018), comprising 150 samples with 4 features and 3 classes, for which we use 4 qubits with angle encoding. The second task is Wine, comprising 178 samples with 13 features (reduced to 4 via principal component analysis (PCA)) and 3 classes, for which we use 4 qubits with angle encoding. The third task is MNIST-4, a subset of MNIST containing digits 0, 1, 2, 3, with images downsampled to 4 × 4 pixels and encoded via amplitude encoding into 4 qubits, yielding 4,000 training samples and 1,000 test samples.

For all experiments, we use a variational circuit consisting of L = 4 layers, where each layer comprises single-qubit R y and R z rotations on all qubits followed by a ring of CNOT entangling gates. The total number of trainable parameters is p = 2 n L = 32 for n = 4 qubits. The observable is a sum of Pauli-Z operators on all qubits: O ̂ = ∑ j = 1 n Z j. The measurement outcome is passed through a softmax layer to produce class probabilities, and the model is trained using cross-entropy loss with the Adam optimizer (learning rate η = 0.01) for 200 epochs.

We compare four implementations. TFQ-native uses TensorFlow Quantum with Cirq circuits and TFQ’s built-in parameterized quantum circuit (PQC) layer (tfq.layers.PQC). PennyLane-native uses PennyLane with the default.qubit device and PennyLane’s built-in qml.qnn.TorchLayer. Qiskit-native uses Qiskit Machine Learning with the EstimatorQNN class and the Qiskit Aer simulator. Ours denotes our framework-agnostic QNN, tested with all three framework adapters (TF, Torch, JAX).

All experiments are conducted on a single machine with an NVIDIA A100 GPU (40 GB), 128 GB RAM, and an AMD EPYC 7763 processor. Quantum circuits are evaluated using the respective framework’s statevector simulator; hardware results are reported separately in Section 8.

7.2 Classification accuracy

Table 4 reports the test accuracy for each framework and dataset combination. Our framework achieves accuracy within the range of native implementations, with differences well within stochastic variation across random seeds (± 1.5 % standard deviation), confirming that the abstraction layer does not degrade model quality.

TABLE 4. Test accuracy (%) on three classification benchmarks. Results are averaged over 5 random seeds; ± values denote standard deviation.

These results are expected: the classification accuracy is determined by the circuit architecture, the optimizer, and the dataset, none of which vary across implementations. The minor variations ( ≤ 0.3 % ) are consistent with stochastic effects from random initialization and mini-batch ordering.

7.3 Training time

Table 5 reports the wall-clock training time for 200 epochs on each benchmark. Figure 5 shows equivalent loss convergence trajectories across the Qiskit, Cirq, and PennyLane execution routes, confirming that the per-epoch overhead does not distort the optimization dynamics.

TABLE 5. Training time (seconds) for 200 epochs on three classification benchmarks. Values are averaged over 5 runs.

The overhead introduced by our framework adapters is modest. For the Iris benchmark, the TF adapter adds 5.9% overhead relative to TFQ-native, the Torch adapter adds 6.5% relative to PennyLane-native, and the JAX adapter adds 1.0% relative to PennyLane-native. On the larger MNIST-4 benchmark, the overhead is 5.9%, 5.8%, and 1.1% respectively. The JAX adapter achieves the lowest overhead because JAX’s functional transformation model aligns closely with our framework’s internal representation, minimizing the cost of parameter conversion and gradient injection.

7.4 Encoding overhead

Table 6 reports the per-sample encoding overhead for each encoding strategy, measured as the wall-clock time to construct the encoding circuit and evaluate it on the simulator.

TABLE 6. Per-sample encoding time (milliseconds) for each encoding strategy on 4-qubit circuits, averaged over 1,000 samples.

Angle encoding is the fastest, as expected, with a circuit build time of 0.11 ms per sample. Amplitude encoding is the most expensive due to the recursive decomposition of multiplexed rotations. IQP encoding with three repetitions ( r = 3 ) approaches the cost of amplitude encoding but provides substantially richer feature maps [Havlíček et al., 2019].

7.5 Counterarguments

Three counterarguments merit consideration. First, one might argue that the overhead introduced by any abstraction layer, however small, is unacceptable for time-critical quantum applications. We acknowledge this concern but note that the bottleneck in hybrid quantum-classical workflows is overwhelmingly the quantum circuit execution (whether on hardware or on a high-fidelity simulator), not the classical parameter conversion. Our overhead (1%–7%) is negligible relative to QPU queue times, which typically range from seconds to hours.

Second, one might question whether framework-agnosticism is necessary when PennyLane already provides multi-backend support. While PennyLane’s plugin architecture is commendable, it requires users to adopt PennyLane’s programming model and quantum function syntax. Researchers with existing codebases in TensorFlow or PyTorch must rewrite their classical pre-processing and post-processing pipelines to integrate with PennyLane. Our approach, by contrast, allows the quantum layer to be embedded directly in native TensorFlow, PyTorch, or JAX code without adopting a new programming paradigm.

Third, the practical utility of our framework depends on the assumption that hardware access is a genuine bottleneck. As quantum cloud platforms mature and adopt standardized APIs, the value of a custom HAL may diminish. We view this as a feature, not a limitation: if the quantum industry converges on a standard API, our HAL can be simplified to a thin wrapper around that standard, and the framework-level and encoding-level contributions will remain fully relevant.

8 Hardware validation

8.1 Experimental configuration

To validate our framework on real quantum hardware, we conducted gradient estimation experiments on two IBM QPU backends. The primary validation uses a 4-qubit variational circuit on IBM ibm_fez, a 156-qubit Heron r2 processor, which provides a rigorous test of multi-qubit gate error pathways. An initial 2-qubit pilot on IBM Brisbane, a 127-qubit Eagle r3 processor (Kim et al., 2023), motivated this extended validation after revealing a qubit-specific calibration artefact.

8.1.1 4-Qubit experiment (IBM ibm_fez)

We constructed a 4-qubit variational circuit with two R y layers (8 parameters total), a CNOT entangling chain ( 0 → 1 → 2 → 3 ), and parameter values θ = ( 0.3 , 0.7 , 1.2 , 0.5 , 0.8 , 1.5 , 0.2 , 0.9 ). The observable is the probability of measuring | 0000 〉. Parameter-shift gradients are computed for the first four parameters (θ 0–θ 3), each using 8,192 shots per shifted circuit.

8.1.2 2-Qubit pilot (IBM Brisbane)

We constructed a 2-qubit variational circuit consisting of an angle encoding layer followed by two variational layers, each comprising R y rotations and a CNOT entangling gate. The circuit has p = 4 trainable parameters. The observable is O ̂ = Z 0 ⊗ I 1, measuring the Pauli-Z expectation value on the first qubit. The parameter vector was set to θ = ( π / 4 , π / 4 , π / 4 , π / 4 ).

8.1.3 Supplementary circuits

To characterize the baseline gate error rate on ibm_fez, we additionally execute a Bell state circuit (2-qubit, fidelity 0.978), a GHZ-4 circuit (4-qubit, fidelity 0.929), and an identity circuit (U U † on 4 qubits, | 0000 〉 fidelity 0.985). These circuits provide reference noise levels for interpreting gradient discrepancies.

For each parameter θ j, we estimated the gradient using the parameter-shift rule (Equation 1) with 8,192 measurement shots per circuit evaluation. The simulator reference was computed using exact statevector simulation (no shot noise, no hardware noise).

8.2 Results

8.2.1 4-Qubit validation (IBM ibm_fez)

Table 7 reports gradient estimates from the 4-qubit experiment on ibm_fez (job d78cgnoeecps73d710j0). All four gradients agree with the simulator within absolute errors of 0.000–0.013, yielding a mean absolute error (MAE) of 0.005. This is consistent with the predicted noise budget and confirms that the HAL correctly mediates between the abstract circuit representation and the backend-specific compiled circuit.

TABLE 7. Parameter-shift gradient estimates on IBM ibm_fez (156 qubits, Heron r2) versus simulator for a 4-qubit variational circuit with 8 parameters (4 April 2026). Physical qubits: 2-qubit circuits → (Q22, Q23), 4-qubit circuits → (Q16, Q21, Q22, Q23). Gradients are computed for θ 0–θ 3; 8,192 shots per shifted circuit. The mean absolute error of 0.005 is consistent with the predicted noise budget (job d78cgnoeecps73d710j0).

8.2.2 2-Qubit pilot (IBM Brisbane)

An initial pilot experiment on Brisbane motivated the 4-qubit validation. Table 8 reports the 2-qubit gradient estimates and Figure 6 visualizes the comparison.

TABLE 8. Parameter-shift gradient estimates on IBM Brisbane (127 qubits, ibm_brisbane) versus simulator (28 February 2026). Physical qubits assigned by Qiskit transpiler; 8,192 shots per shifted circuit evaluation. The parameter vector is θ = ( π / 4 , π / 4 , π / 4 , π / 4 ).

Three of the four gradient estimates (θ 2, θ 3, θ 4) agree with the simulator prediction within absolute errors of 0.035–0.043, which is consistent with the combined effects of shot noise, gate errors, and readout errors on IBM Brisbane. The θ 1 gradient exhibits a larger discrepancy ( | Δ | = 0.528 ), which we attribute to the position of this parameter in the circuit: θ 1 governs a rotation that precedes the entangling gate, and its gradient is therefore more sensitive to two-qubit gate errors (CNOT error rate ≈ 1.2 % on the utilized qubit pair). To confirm this was a qubit-specific artefact, we repeated the identical 2-qubit gradient experiment on three separate qubit pairs on ibm_fez (Q22–Q23, Q0–Q1, Q50–Q51; 8 April 2026). All three pairs yielded mean absolute errors of 0.015–0.069, with no anomalous θ 1 discrepancy on any pair, confirming that the original Brisbane anomaly was qubit-pair-specific rather than a systematic framework defect.

8.3 Noise analysis

To characterize the noise contribution, we decompose the total gradient error into three components: shot noise, gate noise, and readout noise. The shot noise contribution for K measurement shots is bounded by Equation 12:

σ shot = 1 K = 1 8192 ≈ 0.011 . (12)

The gate noise contribution depends on the number of two-qubit gates in the circuit and the average CNOT error rate ϵ CX. For our 2-qubit circuit with 2 CNOT gates per evaluation, the expected gate noise is given by Equation 13:

σ gate ≈ 2 n CX ϵ CX ≈ 2 × 2 × 0.012 = 0.048 . (13)

The readout error rate on IBM Brisbane is approximately ϵ RO ≈ 0.8 % per qubit, contributing (Equation 14):

σ RO ≈ n ϵ RO = 2 × 0.008 = 0.016 . (14)

The total expected noise is therefore σ total ≈ σ shot 2 + σ gate 2 + σ RO 2 ≈ 0.052, which is consistent with the observed errors for θ 2, θ 3, and θ 4. The anomalous error for θ 1 ( | Δ | = 0.528 ≫ σ total ) exceeds the predicted noise by an order of magnitude, suggesting a qubit-specific calibration issue on the Brisbane qubit pair used for the first CNOT gate. This hypothesis is confirmed by the follow-up experiment: repeating the identical 2-qubit circuit on three different ibm_fez qubit pairs (Q22–Q23, Q0–Q1, Q50–Q51; 8 April 2026) yielded mean absolute errors of 0.015, 0.069, and 0.050, respectively, with no θ 1 anomaly on any pair. The 4-qubit experiment (Table 7) independently confirms this finding with a mean | Δ | = 0.005. Temporal drift in qubit calibration parameters is a known source of such outliers on NISQ devices (Kim et al., 2023). Error mitigation techniques (Temme et al., 2017; Endo et al., 2018) could reduce such discrepancies and represent an important direction for integration with our HAL.

8.4 Cross-backend gradient comparison

To demonstrate the HAL’s ability to produce consistent results across backends, we repeated the gradient experiment on the IonQ Harmony simulator (11 qubits, all-to-all connectivity) and the Rigetti Ankaa-3 simulator (84 qubits, square-lattice connectivity). Table 9 reports the gradient vectors obtained from each backend’s simulator.

TABLE 9. Gradient vectors from three backend simulators for the same 2-qubit variational circuit. All simulators agree to within numerical precision ( < 1 0 − 12 ), confirming that the HAL’s transpilation preserves circuit semantics.

The perfect agreement across all three simulators confirms that the HAL’s transpilation engine correctly preserves the circuit semantics when translating between gate sets and qubit topologies. This result is a necessary condition for meaningful cross-hardware comparisons: any differences observed in QPU results can be confidently attributed to hardware noise rather than framework artefacts.

8.5 Cross-vendor QPU validation

To validate the HAL on real quantum hardware beyond a single vendor, we execute the same 4-qubit variational circuit on four QPU backends spanning two qubit technologies: three superconducting processors, namely, IBM ibm_fez (156 qubits, Heron r2, N shots = 8,192), Rigetti Ankaa-3 (84 qubits, N shots = 4,096), and IQM Garnet (20 qubits, N shots = 4,096), and one trapped-ion processor, IonQ Forte-1 (36 qubits, N shots = 4,096). IBM experiments were submitted via Qiskit Runtime; Rigetti, IQM, and IonQ experiments were submitted via Amazon Braket. Table 10 reports state fidelity, the total variation distance (TVD) of the variational output distribution, and gradient accuracy for each backend.

TABLE 10. Cross-vendor QPU validation of the framework-agnostic QNN (4 April 2026). Bell and GHZ-4 state fidelities, variational circuit TVD, and parameter-shift gradient MAE across four QPU backends. IBM ibm_fez: physical qubits (Q22, Q23)/(Q16, Q21–Q23), job d78cgnoeecps73d710j0, 8,192 shots; Rigetti Ankaa-3, IQM Garnet, IonQ Forte-1 via Amazon Braket, 4,096 shots×10 tasks each. Note: IBM fidelities for qubit pair (Q22, Q23)/(Q16, Q21–Q23) differ from those obtained on qubit pair (Q0, Q1) in a separate job submission; the difference reflects qubit-pair-dependent error rates on the same processor.

Across all four vendors, spanning both trapped-ion and superconducting transmon backends, the parameter-shift gradients agree with noiseless simulation to within MAE ≤ 0.007 on every device. The trapped-ion IonQ Forte-1 achieves the highest state-preparation fidelities (F Bell = 0.979, F GHZ - 4 = 0.960) with a gradient MAE of just 0.003, while the superconducting Rigetti Ankaa-3 exhibits fidelities of F Bell = 0.926 and F GHZ - 4 = 0.811, consistent with its higher two-qubit gate error rates. IQM Garnet achieves F Bell = 0.892 and F GHZ - 4 = 0.863, competitive with its reported median two-qubit gate fidelity, and its parameter-shift gradient MAE of 0.007 is in line with the other three backends. IBM ibm_fez experiments were executed via Qiskit Runtime (job d78cgnoeecps73d710j0); Rigetti, IQM, and IonQ experiments were submitted via Amazon Braket (task IDs listed in the supplementary data repository). This cross-vendor agreement provides direct evidence that the HAL and transpiler preserve circuit semantics on production quantum hardware, independent of the native gate set.

9 Discussion

The results presented in Sections 7, 8 demonstrate that framework-agnostic quantum neural networks are both feasible and practical, with measurable overhead that remains negligible relative to quantum circuit execution costs.

The classification benchmarks confirm that our abstraction layer introduces no statistically significant degradation in model accuracy. Across three datasets and four framework configurations, the maximum accuracy difference is 0.3 percentage points, well within the standard deviation of repeated trials. The training time overhead of 1%–7% is attributable to the parameter conversion and gradient translation steps, which operate on small tensors (32 parameters) and are dwarfed by the statevector simulation cost.

The hardware validation results on IBM ibm_fez provide the strongest single-vendor evidence that the HAL correctly mediates between the abstract circuit representation and the backend-specific compiled circuit: all four parameter-shift gradients agree with noiseless simulation within a mean absolute error of 0.005. The earlier 2-qubit pilot on IBM Brisbane yielded agreement for three of four parameters (within σ total ≈ 0.052), with the anomalous θ 1 error attributed to a qubit-specific calibration artefact rather than any systematic framework defect. This observation motivates future integration of real-time calibration data into the backend selection scoring function.

The cross-backend simulator comparison (Table 9) provides the strongest evidence for the HAL’s correctness: all three simulators produce identical gradient vectors to within machine precision ( < 1 0 − 12 ), confirming that the transpilation engine preserves circuit semantics across different gate sets and topologies. The cross-vendor QPU results (Table 10) extend this finding to real hardware: gradient accuracy is maintained across four independent quantum processors from different vendors, spanning both superconducting and trapped-ion technologies.

9.1 Comparison with prior work

Our encoding and gradient machinery builds on established results. Amplitude encoding uses the uniformly controlled (multiplexed) rotation decomposition introduced by Möttönen et al. (Möttönen et al., 2004) and developed for general state preparation by Shende et al. (Shende et al., 2006) and by Plesch and Brukner (Plesch and Brukner, 2011). Our contribution is not a new decomposition but a framework-agnostic abstraction that delegates state preparation to each backend’s native synthesizer while certifying unitary equivalence through Equation 10. Gradient evaluation uses the parameter-shift rule (Mitarai et al., 2018; Schuld et al., 2019), with the stochastic and generalized variants of Banchi and Crooks (Banchi and Crooks, 2021) available when a gate does not admit a two-term shift. The novelty of the present work is the unification of these primitives behind a single interface, so that an identical model definition, its parameters, and its gradients are reproduced across TensorFlow, PyTorch, and JAX and across four quantum processors from different vendors. The contribution is this unification, not any individual primitive in isolation.

These costs are consistent with the broader literature. The multiplexed-rotation state preparation we adopt has a circuit depth that grows linearly in the state dimension, in line with the general synthesis bounds of Shende et al. (Shende et al., 2006); later constructions reduce this depth, with the divide-and-conquer method of Araujo et al. (Araujo et al., 2021) reaching polylogarithmic depth through additional ancilla qubits and the construction of Zhang et al. (Zhang et al., 2022) attaining the optimal depth for arbitrary states. The framework leaves these scalings unchanged, since it delegates state preparation to each backend’s native synthesizer and adds only the bookkeeping needed to certify equivalence across backends. For gradient evaluation, the two-term parameter-shift rule uses two circuit evaluations per parameter (Schuld et al., 2019), and the generalized rules of Wierichs et al. (2022) show that this count is set by the spectrum of the gate generator rather than by the host framework, which is why the gradient cost is identical under TensorFlow, PyTorch, and JAX. For transpilation, the gate counts and depths in Table 11 lie within the range reported by cross-tool benchmark suites such as MQT Bench (Quetschlich et al., 2023). The training-time overhead of 1%–7% therefore reflects the classical bookkeeping around circuit execution rather than the quantum computation, so the asymptotic complexity is unchanged even though the measured cost varies with the framework and the device.

TABLE 11. Transpilation comparison between the Qiskit transpiler (optimization level 3) and t|ket〉 (Sivarajah et al., 2020) for three representative circuits, each compiled to the IBM Heron native gate set { R z , X , X , C Z } on a heavy-hex linear coupling map. Lower is better in every column.

9.2 Relationship to quantum circuit compilers

The hardware abstraction layer operates at the framework-abstraction level and is complementary to, rather than a replacement for, circuit compilers such as t|ket〉 (Sivarajah et al., 2020) and the Qiskit transpiler. Table 11 compares the two compilers on three representative circuits, each rebased to the IBM Heron native gate set { R z , X , X , C Z } on a heavy-hex linear coupling map for a like-for-like comparison. The two compilers are competitive, each winning on different metrics: t|ket〉 achieves a shorter compile time on the entanglement-free angle circuit and produces slightly fewer two-qubit gates on the variational circuit (40 versus 44), whereas the Qiskit transpiler produces fewer two-qubit gates on the IQP circuit and lower circuit depth on both the IQP and variational circuits in this configuration. Because the framework treats circuit compilation as a pluggable stage, it can delegate routing and optimization to whichever compiler is more effective for a given circuit and target, while the gradient and parameter semantics it guarantees remain independent of that choice. This comparison concerns compilation metrics only and is not a statement about runtime quantum performance, which is governed by device noise.

9.3 Run-to-run and cross-device gradient stability

To quantify the statistical stability of the hardware results, we repeated the full 4-qubit parameter-shift gradient estimation five times on each of three IBM Heron r2 processors. Table 12 reports the mean absolute error against exact statevector simulation as mean ± standard deviation over the five repetitions: 0.0063 ± 0.0005 on ibm_fez, 0.0045 ± 0.0006 on ibm_marrakesh, and 0.0032 ± 0.0010 on ibm_kingston. The small standard deviations show that the agreement between hardware and simulation is stable across repeated submissions rather than the product of a single favorable run, and the consistency across three independently calibrated devices indicates that the result is not specific to one processor.

TABLE 12. Run-to-run and device-to-device stability of parameter-shift gradient estimation. The 4-qubit, 8-parameter circuit was executed five times on each IBM Heron r2 processor, with 8,192 shots per shifted circuit. The mean absolute error (MAE) against exact statevector simulation is reported as mean ± standard deviation over the five repetitions.

9.4 Practical performance across frameworks and hardware

Although the asymptotic complexity of a QNN is fixed by its circuit, the observed cost varies with both the host framework and the target device, and our measurements quantify that variation. At the framework level, the training-time overhead relative to a native implementation ranges from approximately 1.0% with the JAX adapter to 6.5% with the PyTorch adapter (Table 5), reflecting differences in autograd bridging and tensor conversion rather than any difference in the quantum computation. At the hardware level, state-preparation fidelity varies with device error rates (Bell fidelity from 0.892 to 0.979), while the parameter-shift gradient MAE against simulation remains uniformly low, from 0.003 on the trapped-ion IonQ Forte-1 to 0.007 on the superconducting IQM Garnet (Table 10). A practitioner can therefore hold the algorithm fixed and attribute observed performance differences to the framework or the device, which is the central purpose of removing vendor lock-in.

9.5 Applicability to neutral-atom and photonic platforms

The present framework targets the gate-based circuit model, and all hardware reported here is gate-based superconducting or trapped-ion. Extending the abstraction to neutral-atom and photonic platforms raises distinct challenges. Neutral-atom processors based on Rydberg interactions expose analog Hamiltonian evolution and global entangling operations rather than arbitrary pairwise gates, so an adapter would need to compile gate-model circuits into a constrained native instruction set or expose the analog interface directly. Photonic platforms, whether continuous-variable or measurement-based, replace the fixed qubit register and discrete gate set with mode-based operations and measurement-driven computation, which do not map onto the unitary-equivalence check of Equation 10 without modification. A practical route to supporting these platforms is to target an intermediate representation such as that promoted by the QIR Alliance, allowing the framework to emit a common representation that platform-specific backends lower to their native primitives.

9.6 Reproducibility

To support independent replication, we record the complete experimental configuration. All software was pinned to fixed versions of Qiskit, qiskit-ibm-runtime, PennyLane, TensorFlow, PyTorch, and JAX. Classification benchmarks were averaged over five random seeds with fixed train and test splits. Hardware experiments are identified by their provider job identifiers so that they can be verified against provider records: the 4-qubit ibm_fez validation is job d78cgnoeecps73d710j0, and the repeated-run stability experiments are jobs d8lu773nn5bs738skjsg on ibm_fez, d8lu8sbqv2lc73870ai0 on ibm_marrakesh, and d8lu8t832u0s73fag500 on ibm_kingston.

10 Conclusion

We have presented a framework-agnostic quantum neural network architecture that addresses vendor lock-in along three axes: framework-level integration, hardware abstraction, and encoding-level equivalence. Our multi-framework architecture enables a single QNN definition to be trained and evaluated using TensorFlow, PyTorch, or JAX without code modification, through framework adapters that translate parameters, gradients, and loss functions between the QuantumLayer’s internal representation and the host framework’s autograd engine. The hardware abstraction layer provides a unified API for circuit submission across IBM Quantum, Amazon Braket, Azure Quantum, IonQ, and Rigetti backends, with automatic transpilation that preserves circuit semantics. Three pluggable data encoding strategies (amplitude, angle, and IQP) are verified to produce identical quantum states across all supported backends. The export pipeline, augmented with ONNX metadata extensions for quantum operations, enables lossless circuit translation with round-trip fidelity exceeding 0.9999.

Benchmark experiments on three classification tasks demonstrate that our framework achieves classification accuracy indistinguishable from native framework implementations, with training time overhead between 1% and 7%. Hardware validation on IBM ibm_fez confirms that parameter-shift gradients computed through the HAL are consistent with simulator predictions within noise margins. Cross-vendor QPU experiments on four backends (IBM, Rigetti, IQM, IonQ) spanning both superconducting and trapped-ion technologies show gradient MAE ≤ 0.007 on all four backends, and cross-backend simulator comparisons verify that the transpilation engine preserves circuit semantics to numerical 8 for future work merit investigation. First, the extension of our ONNX schema to support a wider range of quantum operations, including mid-circuit measurements and classical feedforward, would enable support for dynamic quantum circuits. Second, integration with emerging quantum error correction codes would extend the framework’s relevance beyond the NISQ era. Third, the development of automated encoding selection strategies, which analyze the structure of the input data and recommend an optimal encoding, could further reduce the burden on the practitioner. Fourth, as quantum hardware matures and standardized APIs emerge through initiatives such as the Quantum Intermediate Representation (QIR) Alliance, our HAL’s architecture should evolve to build on these standards rather than maintaining independent provider-specific adapters.

Vendor lock-in in quantum machine learning is a technical impediment to reproducible science: when models cannot be transferred between frameworks and hardware platforms, observed performance differences may reflect framework overhead rather than algorithmic merit. The architecture described here removes that impediment, enabling benchmark comparisons grounded in hardware rather than software choice, and opening a path to genuinely portable quantum machine learning research.

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Footnotes

Edited by: Roopayan Ghosh, Indian Institute of Technology Bhubaneswar, India

Reviewed by: Chukwudubem Umeano, University of Exeter, United Kingdom

Ernane Jose Xavier Costa, University of São Paulo, Brazil