Low-loss power management strategy for weak and low-frequency biomechanical energy harvesting for new generation wearable electronics

1 Introduction

The power management circuit (PMC) plays a vital role in realizing the integration of renewable energy sources with energy storage systems, enabling efficient energy transfer to address the rising energy demand for new generation wearable electronics (Faisal et al., 2018; Xu et al., 2014; Abhinav and Pindoriya, 2016; Kaper and Choudhary, 2016; Nouri et al., 2024; Abdelsattar et al., 2024). Biomechanical energy harvesters (BEH), first reported in 2012 (Fan et al., 2012), convert ambient mechanical energy into electricity using electrification and electrostatic induction effects, offering a promising weather-independent and compact energy alternative compared to other renewable energy sources (Jiang et al., 2015; Wang, 2019; Zi and Wang, 2017; Zhang H. et al., 2024). However, as the device responds to external stimuli, the varying frequency and magnitude of mechanical energy inputs result in fluctuations in electricity generation, causing difficulties in energy integration and storage. Moreover, the typically high output voltage (up to kV-level), weak output current (μA-level), and AC outputs of BEH restricts their use as direct power sources or for battery charging, where a relatively low-voltage (V-level), high-current (mA to A-level), and DC electricity source is required. The mismatch between BEH sources and terminal appliances reduces the energy extraction and transfer efficiency, resulting in considerable energy loss. To address this problem, the integration of PMC is essential.

To date, PMCs have been studied for AC/DC conversion and capacitor charging when operating with a relatively greater current output from high-frequency BEH sources (Niu and Wang, 2015; Shankaregowda et al., 2016; Lee et al., 2014; Zhang Z. et al., 2024; Zhou et al., 2023; Wang et al., 2023). However, commercial full-wave bridge rectifier and capacitors often experience leakage currents, which can result in circuit failure when the current output from low-frequency BEH sources is much lower. This simple topology works well to temporarily store energy in capacitors for powering portable electronics, such as smartwatches and humidity meters (for seconds). However, its energy extraction and transfer efficiencies are very limited due to the mismatch between the internal impedance of BEH sources and external circuit load. Resistor-inductor-capacitor (RLC) impedance matching circuits with buck conversion functionality have been researched to improve energy extraction (Zhang Z. et al., 2024; Fang et al., 2020; Zhao et al., 2017; Kong et al., 2010; Wang et al., 2015). Inductors function in discontinuous mode, when their current direction changes within a single switch on-and-off cycle (Supplementary Figure S1), leading to an RLC series resonance phenomenon under light-loading (≤30%) or no-loading. Its pulse current and voltage electromagnetically interact with the BEH source, resulting in greater ripple, which requires additional filtration, resulting in energy loss and reduced energy transfer efficiency. In summary, BEH for battery charging has been minimally studied. Less efficient RLC impedance matching and high energy loss due to inappropriate component sizing reduce energy extraction and transfer efficiencies, respectively (Kong et al., 2010; Shi et al., 2022).

A low-loss PMC (L-PMC) technique is explored in this study for the purpose of weak biomechanical energy harvesting at low-frequency. Since the current and intermittence of BEH affect circuit efficiency and are determined by the operating frequency, we studied the PMC under extreme conditions at 1 Hz. The objective is to realize battery charging by reducing current ripple and energy loss, while attaining efficient energy extraction and transfer efficiency to fulfil the requirements of a reliable and readily available DC power source. This work incorporates two PMC topologies, as seen on Figure 1. Topology_1 is a 2-stage RC impedance matching circuit with buck conversion functionality. The analyzed Topology_1 achieves an energy extraction efficiency of 42.24% and can charge a battery to 20% in 10 min at a low operating frequency of 1 Hz. Topology_2 is a multi-capacitor unit for current amplification, further enhancing the energy transfer efficiency from 30.59% to 63.55%, representing 207% enhancement. The study is conducted in three phases: 1) mathematical derivation for impedance matching, 2) circuit topology design and simulation, and 3) experimental validation.

2 Materials and methods

2.1 Biomechanical energy harvester

A 3 cm × 3 cm contact-separation BEH device was fabricated as the power input of the PMC, with working principle as shown in Figure 2A (Wang et al., 2020). The device features Au/PEI/PVA as the tribo-positive layer, PET as the tribo-negative layer, and PET-ITO as the top and bottom electrodes. The device was packaged using Kapton tape, with a 2 mm air gap between the triboelectric layers. Upon pressing and releasing the device, the PET and Au/PEI/PVA layers became negatively and positively charged, respectively, due to their differing electronegativity. Externally, electrons flowed between the top to bottom electrodes, and the cyclic operating mode of the device resulted in an AC power output.

2.2 Measurements

The output performance of the BEH was measured using source meters (Keithley 2400 and 6514) and a low-noise current preamplifier (SR570). A linear motor (LinMot) supplied biomechanical energy. The device output was measured at 1 Hz, with a positioning movement of 0.015 m per cycle, an acceleration of 1 m/s², and a maximum speed of 1 m/s. PMC performance was simulated using NI Multisim, LTspice, and MATLAB simulink. The BEH output remained steady after 1,250 cycles, with an open-circuit voltage of 65 V, a short-circuit current of 3.3 μA, and a power density of 108.33 mW/m², as shown in Figures 2B, C. Operating frequency greatly affected device output. Supplementary Figures S2, S3 show device’s output under different operating frequencies ranging from 0.5 to 5 Hz. This study only considers low-frequency conditions and thus operates at a frequency of 1 Hz unless stated otherwise.

2.3 Mathematical derivation for impedance matching

Due to the capacitive property of BEH, its huge internal impedance makes it difficult to output power on the external load without a well-considered impedance matching. To study this process, consider an equivalent circuit as shown in Figure 2D. The AC power source is ideal with an internal impedance of Z 0 and an external load impedance of Z L. To be universally applicable, both Z 0 and Z L consist of two components: resistance (R) and reactance (X) in Equations 1, 2.

Internal impedance : Z 0 = R 0 + j X 0 (1)

External impedance : Z L = R L + j X L (2)

According to Ohm’s Law and voltage division principle, load voltage and load current can be derived in Equations 3, 4. The output power on load can be calculated using Equation 5.

V L = Z L Z 0 + Z L V 0 (3)

I L = V L Z L = Z L V 0 Z 0 + Z L Z L (4)

P L = V L I L = Z L V 0 Z 0 + Z L × Z L V 0 Z 0 + Z L Z L = Z L V 0 2 Z 0 + Z L 2 (5)

A = Z 0 Z L (6)

K = A A + 1 2 (7)

P L = V 0 2 Z 0 × A A + 1 2 = V 0 2 Z 0 × K (8)

The varied A is used to denote the ratio between Z 0 and Z L in Equation 6. As V 0 and Z 0 are determined by the device itself and can be regarded as constants, the multiplication constant of K in Equation 7 is introduced to facilitate comparison among various impedance matching strategies. The power input on external load in Equation 5 can be further expressed by Equation 8.

2.3.1 RLC complex conjugate matching

The maximum power on loads of an RLC matching circuit occurs when the load impedance is the complex conjugate of the source impedance for a fixed AC source (Kong et al., 2010; Niu et al., 2014), which is an ideal result. The external impedance under complex conjugate matching process can be further described as:

External load impedance : Z L = R 0 − j X 0 (9)

According to Equations 8, 9, the theoretical maximum power on external load can be derived in Equation 10:

P L , c o n j u g a t e = V 0 2 Z 0 × K = V 0 2 4 Z 0 (10)

According to Equation 7, K for RLC complex conjugate matching is 0.25 with A equals to 1, as shown in Figure 3A.

2.3.2 Resonance RLC matching

Resonance RLC matching is studied to achieve theoretical maximum power on external load, where the reactance of inductor and capacitor is equal. The relationship of L and C in this case is described by Equation 15

X C = 1 ω C = 1 2 π f C (11)

1 X C ∝ f (12)

X L = ω L = 2 π f L (13)

X L ∝ f (14)

f = 1 2 π L C (15)

I L e a k a g e = k × C × U (16)

With a fixed operating frequency of 1 Hz, the empirical formula for capacitor leakage current in Equation 16 states that the constant of current leakage (k) is equal to 0.003 for electrolytic capacitors in industries (Shi et al., 2022). Here, C represents the capacitance of the capacitor and U is the rated voltage of the capacitor. With U in the hundreds of volts, to ensure that the capacitor leakage current does not result in circuit failure, only capacitors with C no larger than μF and a I L e a k a g e no larger than μA can be used for BEH applications. In this case, RLC resonance can only be achieved when the inductance (L) is more than 20 kH while using a μF-capacitor; however, this configuration would occupy too much space for wearable and portable electronics.

2.3.3 Proposed RC matching

To simulate the output of the BEH, its average voltages were calculated and used to generate a pulse signal, shown by the red line in Figure 3C. To enhance the uniformity of the simulated pulse signal, a pulse voltage source with a pulse value of 48 V and a duty ratio of 43% was used for simulation, as shown by the blue line. Figure 3D shows the current ripple elimination through the proposed RC impedance matching. By taking out the inductor from the RLC (which operates in a discontinuous mode) and adding a capacitor for energy storage and filtering, the proposed RC impedance matching enhances the stability of the output. This modification helps prevent capacitor failure and improves the efficiencies of energy transfer and extraction. According to Equations 11–15, the reactance depends on operating frequency, as shown in Figure 3B, with a capacitance of 1 μF and an inductance of 20 kH. When operating under a very low frequency, the X C is significantly greater than X L. The RC strategy’s K is very close to 0.25. This proposed RC strategy can achieve a power output that is closer to the theoretical maximum while also being suitable for practical applications.

3 Results

3.1 Circuit topology design and simulation

The RC circuit topology design is examined from two specific perspectives, namely, the resistive load (R) and the capacitive load (C), to minimize energy loss and maximize power production. Various permutations and combinations of R and C result in distinct circuit topologies and varying load impedances (Z L), as summarized in Table 1. The characterization of Z L can be further refined based on the RC load behavior during low-frequency operation. Equation 11 states that X L , C approaches infinity at low frequencies, providing a significant advantage over R L and exerting a major impact on the Z L of the second and third topologies in Table 1. In contrast, when components are connected in parallel, the impedance of a circuit is mostly determined by the smaller impedance component. Therefore, R L have a significant impact on the first, fourth, and fifth topologies. Thus, to simplify the modelling process, the circuit topologies are categorized into two groups based on their impedance characteristics.

TABLE 1. Mathematical description of load impedance Z L with different circuit topologies.

3.1.1 Powering a resistive load

Using BEH to power a pure resistive external load, the power output on load can be described as:

P L = V L I L = V 0 Z 0 R L + 1 × V 0 Z 0 + R L = V 0 2 Z 0 2 R L + 2 Z 0 + R L (17)

Deriving Equation 17 with respect to R L,

P L R L ′ = V 0 2 Z 0 2 R L 2 − 1 2 Z 0 + R L + Z 0 2 R L 2 (18)

The optimum power on external load can be obtained when Equation 18 equals to ‘0’, which occurs at an external load in Equation 19:

R L = R 0 + 1 j ω C 0 (19)

Therefore, the R L is determined by the operating frequency of the BEH for an optimum matching, lacking universality for circuit applications.

3.1.2 Charging a pure capacitive load

The voltage V t and the current I t are cyclic functions of time for an AC power source.

V t = V p e a k ⁡ sin ω t (20)

I t = d q d t = C d v d t = C c o s ω t (21)

Given Equations 20, 21, the voltage and current consistently exhibit a 90° phase delay, resulting in a total energy buildup of zero on the external load during a single operation cycle. This ineffective charging of the external load highlights the need for an AC/DC conversion circuit. Here, we investigated four specific elements of topology modification to improve the PMC based on the pure capacitive load approach.

3.1.3 Modification with AC/DC conversion

A full-wave bridge rectifier consisting of four diodes is introduced to convert AC electricity into pulsed DC electricity to avoid energy elimination within one operation cycle. The circuit topology is shown in Figure 4A. Instead of using a commercially assembled rectifier designed for power levels ranging from mW to W, we selected four low-loss diodes to match the BEH’s power level of μW. The energy storage on the capacitive load can be described as:

E = 1 2 C V 2 (22)

η = E L E 0 = V L 2 C L V 0 2 C 0 = B C L C 0 (23)

C L is the capacitance of external load, while C 0 is the internal capacitance of BEH. Charging a capacitor is a dynamic process as charge accumulates over time. With continuous device operation, V L theoretically equals to V 0 given adequate charging time. Equation 23 can be simplified by introducing B as a constant factor, defined as V L 2 V 0 2. Thus, the energy extraction efficiency largely depends on C L. However, C L of capacitor cannot be increased infinitely since this can cause excessive current leakage, reducing circuit efficiency and resulting to circuit failure. To assess the circuit performance over a short operation period, the mathematical model must be revised.

C = Q V (24)

Deriving from Equations 23, 24, the energy extraction efficiency can be expressed as:

η = Q L V L Q 0 V 0 (25)

Assuming there is no additional energy loss between the device and the capacitor load. Based on Equation 25, the charge transfer amount is fixed within one operation cycle of the power source, and the efficiency depends on V L.

According to the simulation results with an AC power source of 3 μA and 35 V in Figure 5, an nF-level capacitor demonstrated higher energy extraction efficiency within one operation cycle, particularly with a larger V L, as shown in Figure 5A. The average voltages (V A V E) of various C 1 s t are summarized in Figure 5B. C 1 s t of 1 nF, 10 nF and 33 nF exhibited nearly identical V A V E, indicating that the energy extraction efficiency depends primarily on capacitance, with the 33 nF showing the highest efficiency. For a longer operation period of 30s, C 1 s t ranging from 10 nF to 1 μF achieved equivalent voltage as indicated by their intersection point ‘a’ in Figure 5A, with the 1 μF capacitor demonstrating optimum performance due to its larger capacitance. Experimental validation was conducted for C 1 s t values ranging from 10 nF to 1 μF.

3.1.4 Modification with RC filtration

A switch is used to control the circuit connection between C 1 s t and R L as shown in Figure 4B. C 1 s t is charged by the BEH when the switch was turned off, and discharge to R L when the switch was turned on. The discharging process is affected by the different values of R L, as the power delivered to R L is inversely proportional to its resistance. This resulted in a smoother voltage waveform due to the faster-charging and slower-discharging processes, achieving filtration as shown in Figures 5C, D. Moreover, with a 1 KΩ and 1 MΩ R L, the discharge voltage approaches zero in Figure 5C, indicating that R L was too small compared to the BEH’s internal resistance, and was being short-circuited. From the enlarged voltage waveform in Figure 5C, with a GΩ-level R L, C 1 s t discharged effectively, providing a stable voltage to the circuit. The filtration effects remained consistent across various GΩ-level R L, with nearly identical discharge slopes and output voltages.

As demonstrated by the mathematical model, larger capacitance leads to higher energy transfer efficiency over an extended operation period. A C 1 s t of 33 nF is optimized for the highest energy extraction efficiency within a short operation period (one cycle). Figure 4C introduces a second-level capacitor, designated as C 2 n d, aimed at enhancing energy transfer efficiency increased capacitance.

The simulation results of C 2 n d ranging from 33 nF to 1 mF are shown in Figure 6. C 2 n d demonstrated lower voltage accumulation rate and values with an increase in capacitance (Figure 6A). C 2 n d with a capacitance of 33 nF demonstrate the fastest and highest voltage accumulation. C 2 n d values ranging from 2.2 μF to 33 μF exhibit a slower voltage accumulation with increasing capacitance. C 2 n d values ranging from 47 μF to 1 mF show an invalid energy storage without voltage accumulations, indicating a significant amount of energy loss in terms of current leakage. Moreover, C 2 n d of 0.22 μF, 0.47 μF, and 1 μF reached the same voltage level (around 4 V) in 30s, indicating that the energy transfer efficiency depends on capacitance only in this case, and that C 2 n d of 1 μF has the highest energy transfer efficiency. When comparing the short-time charging performances of 33 nF (maximum voltage accumulation) and 1 μF (highest energy transfer efficiency), there is a 1.2-fold difference in voltage. However, the capacitances differ by a factor of 30.3-fold, indicating that the difference in capacitances have a major effect on the energy transfer efficiency. Thus, 1 μF is identified as the optimum C 2 n d value, providing a balance between charging time and energy transfer efficiency.

3.1.5 Addition of a J-FET transistor switch

The purpose of buck conversion during battery charging in this work is to achieve a safe charging voltage of 3 V. To regulate the voltage, we introduce a J-FET transistor switch, where the voltage division between the gate and drain (V G S) terminals defines its actuated state. L-PMC uses an n-type J-FET in its linear mode as a variable resistor to regulate its voltage. The regulated voltage of C 2 n d load is V C 2 n d. Since the feedback current to JFET is very low (∼nA), R 1 and R 2 can be up to GΩ, leading to less power consumption. During operating cycles, the energy is stored in C 1 s t first, leading to increased V C 2 n d. V G S is reduced as a result of increased V C 2 n d. Thus, drain current decreased, leading to reduced V C 2 n d. Therefore, the circuit can be used to regulate voltage. An R L of 50 GΩ is divided into R 1 and R 2 for voltage division controlling, and the circuit topology is shown in Figure 4D.

According to the simulation results in Figures 6C, D, the switch can effectively regulate V C 2 n d lower than V C 1 s t with an R 1: R 2 ratio of more than 3:2, and larger ratio leads to a better buck conversion performance. On the contrary, the switch has no obvious regulation effect on V C 2 n d with a ratio of R 1: R 2 = 1:9 since the voltage before and after the RC units remains within the same range. With a voltage input of 35 V, the circuit output voltage is controlled to approximately 3 V with a ratio of R 1: R 2 = 9:1, perfectly aligning with the battery charging requirement. With the circuit topology illustrated in Figure 4D, a noisy V C 1 s t of 10 V is transformed to a stable V C 2 n d of 3 V as shown in Figure 6B.

3.1.6 Passive amplification unit

Recently, a charge excitation circuit (CEC) has been proposed to enhance the device’s surface charge density (Wang et al., 2020; Liu et al., 2019; Liu et al., 2020). However, this topology faces challenges related to potential air breakdown. Unlike CEC, the proposed passive amplification strategy using multiple capacitors enhance charge accumulation and amplifies current without introducing any active components which can cause additional energy consumption. The capacitors are charged in series to fully utilize the output from the BEH, and discharged in parallel to achieve a current amplification with a constant discharging voltage. According to the voltage accumulation results of C 1 s t in Figure 6B, the V C 1 s t is approximately 9V, which is 3-fold higher than the V C 2 n d of approximately 3 V, underscoring the feasibility of this approach. The simulation and experimental results for Topology-2 are shown in Figure 8. Voltages from three measuring points (MP1, MP2, and MP3) in Figure 2 were collected to validate the concept. Moreover, voltage, charge, and energy accumulation of Topology_1 and 2 are compared to evaluate the circuit performance.

I = ∆ Q ∆ t = ∆ V C N ∆ t (26)

In Equations 22, 26, N represents the number of the multiple capacitors, and t is the operation period. A 3-fold increment in Q leads to 3-fold increments in I and E with Topology_2, indicating an improved circuit performance.

3.2 Experimental validation of L-PMC

3.2.1 RC filtration circuit

Experimental validation of C 1 s t ranging from 10 nF to 1 μF is shown in Figures 7A–D. C 1 s t of 10 nF demonstrated a highest voltage accumulation within one operation cycle; however, the voltage dropped to around 3 V after 30s, likely due to limited filtration. C 1 s t of 33 nF exhibited the highest voltage accumulation which is stable after long-time charging of 30s. Based on Equation 22, the energy accumulation (E C 1 s t) is summarized in Figure 7C. C 1 s t of 33 nF showed maximized energy storage, approximately 3.75 times higher compared with other capacitors, confirming the simulation results and validating it as the optimized capacitance value in this L-PMC. As for the experimental verification of C 2 n d, the nF-level capacitors showed higher V C 2 n d but lower E C 2 n d in Figures 7E–H. The 0.47 μF capacitor exhibited higher E C 2 n d within 30s but was eventually matched by the 1 μF capacitor after an extended charging period of 160s with a more stable voltage. Thus, 1 μF is identified as the optimum sizing of C 2 n d in this L-PMC, confirming the simulation conclusions.

3.2.2 J-FET switch

V C 2 n d can be effectively controlled with resistor ratios of R 1: R 2 = 3:2, 7:3, 4:1, and 9:1 according to the simulations. A DC power source is used for experimental verification in Figures 7I–L. An R L of R 1: R 2 = 3:2, 7:3, and 4:1 showed effective voltage regulation only when the input voltage was no less than 6 V, indicating an invalid switch and buck conversion for input voltage ranging from 3 V to 6 V. On the contrary, a ratio of R 1: R 2 = 9:1 exhibited effective voltage control with an input voltage larger than 3 V. Thus, R 1: R 2 = 9:1 is identified as the optimal component sizing for R L, confirming conclusions drawn from the simulations.

3.2.3 Passive amplification unit

Three measuring points (MP_1, MP_2, and MP_3) in Figure 2 were selected. MP_3 measures the voltage on a single capacitor, MP_2 measures the voltage on the two series-connected capacitors, and MP_1 measures the voltage on three series-connected capacitors during the charging of the capacitors. Simulation and experimental results of the three MPs are displayed in Figure 8A, where a stable 3 V is observed across each capacitor. Additionally, processed outputs of Topology_1 and 2 are shown in Figures 8B–D. C 2 n d is measured in Topology_1 and MP_1 is measured in Topology_2. The results indicate that the charge and energy accumulation achieved a 3-fold enhancement within 600s of charging. The experimental and simulation results are in high agreement. However, all the experimental results showed a relatively longer time to reach a stable state compared to the simulation results, which may be due to the nonnegligible energy dissipation in the practical charging experiment.

3.3 Circuit efficiency calculation

In summary, the optimal parameters of the L-PMC Topology_1 are C 1 s t = 33 nF, C 2 n d = 1 μF, R L = 50 GΩ with a resistive ratio of 9:1 between R 1 and R 2. Factors including energy extraction efficiency, energy transfer efficiency, and battery charging efficiency are used to evaluate the L-PMC.

3.3.1 Energy extraction efficiency

The energy extraction efficiency refers to the proportion of energy input on loads from the device, which is determined by the PMC matching. The energy extraction efficiency of Topology_1 is compared with other works in Table 2. With a C 1 s t of 33 nF, a stable V C 1 s t of 60.8 V was obtained after 34 cycles. The E C 1 s t is calculated to be 60.995 mJ using Equation 22. The E m shows the inherent characteristic of the device, which depends on the maximum surface charge density, open-circuit voltage, and absolute voltage (Wu et al., 2019). The measured Q s c , ⁡ max, V o c , ⁡ max and V max ′ are 60.48 nC, 58.85 V and 81.6 V, respectively. Based on the same method, E m was calculated to be 4.25 mJ per cycle. The much higher energy extraction efficiency of 42.24% was calculated using the same method as prior works in the table (Zi et al., 2017; Cheng et al., 2017). The calculation details are provided in the supporting information (Supplementary Figure S4).

TABLE 2. Comparison of energy extraction efficiency with published works.

3.3.2 Energy transfer efficiency

Energy transfer efficiency refers to the proportion of energy stored in the second-level capacitor from the energy input on loads (first-level capacitor), which is calculated as 44.05% based on E C 1 s t and E C 2 n d of Topology_1 using Equation 23. Furthermore, a battery is charged from 1.9 V to 2.4 V within 10 min with the L-PMC Topology_1 (Supplementary Figure S6). With Topology_2, the energy transfer efficiency shows 207% enhancement (from 30.59% to 63.55%), with calculation details presented in the supporting information (Supplementary Figure S5).

4 Conclusion

While the milliwatt output level of low-frequency biomechanical energy harvesters makes them appropriate for sensing application, their high voltage, weak current, and AC output restrict their effectiveness as a direct power source. Conventional RLC circuit limits the energy transfer efficiency in biomechanical energy harvesters due to the extremely low circuit current. In this study, a low-loss power management circuit is studied with a well-matched 2-stage energy transfer strategy to minimize energy losses, leading to a much higher energy extraction efficiency of 42.24% compared with previous studies. Furthermore, using Topology_1, a battery was charged from 1.9 V to 2.4 V in 10 min with an energy transfer efficiency of 30.59%. The integration of passive current amplification using Topology_2, a 3-fold enhancement in charge accumulation and energy storage is achieved and the energy transfer efficiency achieves an enhancement of 207%. This enables the effective use of the device as DC power source through integration with a battery, demonstrating potential for application in new generation self-powered wearable electronics.

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Supplementary material

The Supplementary Material for this article can be found online at: https://www.frontiersin.org/articles/10.3389/felec.2025.1501178/full#supplementary-material

Supplementary material Supplementary material at the source