A 98.8%-efficiency, thermally-optimized 48 V-to-12 V DC–DC converter for high-power data centers

1 Introduction

The rapid development of artificial intelligence and cloud computing has substantially increased the demand for high-power processors (XPUs) in data centers. This trend exposes the inherent limitations of conventional low-voltage power delivery architectures, primarily due to excessive transmission losses. In response, the 48 V power delivery architecture has emerged as the mainstream solution, offering reduced distribution losses and higher power density. Current research in this area has mainly focused on vertical power delivery (VPD) optimization, highly efficient coupled inductors, and high-power-density DC–DC converter designs.

In the domain of coupled inductors, a gapless powder-core multiphase integrated transverse-flux negatively coupled inductor has been proposed (Naradhipa and Li, 2025). The design employs single-strand windings to reduce DC resistance (DCR), achieving a four-phase integrated structure with a footprint of only 100 mm² and a height of 2.9 mm, capable of delivering 300 A (75 A per phase) at a current density of 3 A/mm². By leveraging negative electrical coupling, this approach mitigates the symmetrical challenges of high-phase-count directly coupled inductors (DCL). Furthermore, the powder core provides a higher saturation flux density than ferrite, reducing manufacturing complexity and inductance tolerance, while multiphase integration improves the non-coupling inductance from 60 nH to 81 nH.

For diverse 48 V power delivery scenarios, multiple converter topologies have been explored. A dual-bus architecture employing a “four-phase interleaved buck converter cascaded with a 3:1 switched-capacitor converter (SCC)” has been reported (Geng et al., 2025). The front stage achieves 48 V-to-12 V conversion with 25% duty cycle and interleaving control, theoretically eliminating current ripple. The rear stage uses three series capacitors and four parallel MOSFETs per bridge arm to realize 12 V-to-4 V conversion, achieving 0.34 mΩ equivalent resistance at 200A output with a cost of 0.82 €/A, while meeting DOE Level VI standards. The vertical PCB design further enables N+1 redundancy for improved system reliability.

Cascaded resonant SCCs have also been proposed for 48 V-to-12 V intermediate bus conversion. A two-stage prototype achieves 98.94% peak efficiency and a power density of 4700 W/in³ with only two switches and one flying capacitor in the first stage, and a shared resonant inductor between both stages (Ge et al., 2021). Further optimization introduced zero-voltage switching (ZVS) operation, achieving over 97% efficiency at just 3% rated load (1.8A) and reducing switching loss by 50% compared to ZCS mode, without requiring hardware modifications (Ye et al., 2019).

The rationale for employing a resonant switched-capacitor (ReSC) topology lies in its performance benefits for a 4:1 conversion ratio. Compared to an LLC converter, the ReSC structure minimizes switch voltage stress (to ≈36 V versus the full 48 V input), thereby reducing switching losses and boosting efficiency (Zhu et al., 2023a). Furthermore, the ReSC utilizes smaller magnetics for resonance compared to the bulky isolation transformer of an LLC, facilitating a more compact design with higher power density. These characteristics make it a more compelling choice than both LLC and interleaved buck converters for this specific high-step-down application. Beyond the representative examples discussed above, recent studies have further advanced resonant/switched-capacitor converter research for data-center power delivery in topology design, analytical modeling, high-performance implementation, and control/regulation. These efforts include resonant/switched-capacitor topology and analysis developments, high-efficiency converter implementations, and regulation-oriented methods such as autotuning and soft-switching control. Representative works include Ye et al. (2018), Ye et al. (2020), Liu et al. (2020), Liu et al. (2022), Ge et al. (2023), Qiu et al. (2023), Rizzolatti et al. (2023), Balutto et al. (2023), Sambo et al. (2023), Sambo et al. (2025), Elasser et al. (2024), and Guan et al. (2024).

For direct 48 V-to-1V point-of-load (PoL) applications, hybrid switched-capacitor converters demonstrate unique advantages. A representative design combines a “2:1 SCC front-end with two 8:1 series-capacitor buck modules,” which merges bus voltages into two levels, eliminating bulky DC bus capacitors and reducing switch count (Zhu et al., 2023b). This design achieves a 16:1 conversion ratio with a normalized switch VA rating of only 10.2, outputting 500A at 94.7% peak efficiency and 464 W/in³ power density. It also adopts E–I composite magnetic cores for compact anti-coupling inductors and a synchronous bootstrap driving scheme, reducing the total voltage drop of seven driver boards to just 0.7V.

Beyond the representative examples discussed above, recent studies have further expanded the resonant/switched-capacitor converter landscape for data-center power delivery in terms of topology development, analytical modeling, control strategies, and high-performance implementations. Representative examples include a resonant switched-capacitor 4:1 bus converter with very high power density and efficiency (Ye et al., 2018), the cascaded resonant converter as a hybrid switched-capacitor topology with high power density and efficiency (Ye et al., 2020), matrix autotransformer switched-capacitor converter structures for data-center applications (Qiu et al., 2023), and high-performance 3:1 conversion-ratio converter design with modular adoption (Guan et al., 2024). In addition, analytical and control-oriented advances include geometrical state-plane analysis for cascaded multiresonant converters (Ge et al., 2023), improved passive utilization through bi-lateral energy resonant conversion (Liu et al., 2022), quasi-resonant regulation and mismatch-mitigation techniques (Balutto et al., 2023), and autotuning/adaptive zero-current-switching strategies for resonant switched-capacitor converters (Sambo et al., 2023; Sambo et al., 2025). High-efficiency and high-power-density hardware demonstrations have also been reported in two-stage resonant switched-capacitor implementations for data-center applications (Liu et al., 2020), regulated 48 V-to-12 V converter implementations (Rizzolatti et al., 2023), and compact CPU voltage regulator platforms (Elasser et al., 2024).

Nevertheless, challenges remain:magnetic components are constrained by core saturation flux; high step-down converters require multiple capacitors in parallel to mitigate tolerance; cascaded converters face a trade-off between conduction losses at heavy loads and switching losses at light loads. For instance, the dual-bus converter achieves only 85.05% full-load efficiency, with copper loss in inductors and conduction loss in MOSFETs accounting for 70% of total losses. Moreover, PCB copper layers (2 oz) contribute up to 25% of total loss under high current, while high-phase-count control requires further refinement.

Motivated by these challenges, this work proposes a cascaded resonant switched-capacitor converter that steps down 48 V to 12V, incorporating resonant operation and PCB structural optimization. By comparing six-layer and eight-layer PCB prototypes, both simulation and experimental results validate the necessity of substrate optimization. The proposed approach improves the efficiency of switched-capacitor step-down technology and demonstrates the potential of soft-switching techniques for achieving ultra-high power density.

2 Circuit design and analysis

2.1 Switched-capacitor circuit design

The cascaded resonant converter proposed in this work operates on a similar principle to conventional resonant 2:1 switched-capacitor converters. The circuit diagram is shown in Figure 1A. To achieve ultra-high efficiency and stable conversion, all MOSFETs in the converter operate at the same switching frequency with a duty cycle of 50%. The PWM signals are illustrated in Figure 1B. The resonant frequency is determined by the resonant inductance L r and total resonant capacitance C r, calculated as:

f r = 1 2 π L r C r

Each MOSFET is driven by one of two complementary PWM signals, with a dead time of 20–40 ns reserved in each cycle to buffer the transition and prevent shoot-through conduction.

Figures 1C,D illustrate the two operating states within one complete switching cycle. In the first half cycle, the primary LC resonant branch, together with the resonant branch formed by C F 21 and L 21, is connected in series, while the branch consisting of C F 22 and L 22 delivers power to V o u t. In the second half cycle, the branch with C F 22 and L 22 resonates with C F 1 and L 1, while C F 21 and L 21 take over the charging process for V o u t, completing energy transfer and release.

All flying capacitors and resonant inductors are designed with equal capacitance and inductance values, ensuring identical resonant frequencies for both stages. The switching frequency is set equal to the resonant frequency, enabling all MOSFETs to achieve ZCS. This significantly reduces switching loss during MOSFET transitions, thereby improving the overall conversion efficiency.

2.2 PCB design

Heat transfer in PCBs generally occurs through three mechanisms: thermal conduction, convection, and radiation, as illustrated in Figure 2A. This work primarily focuses on enhancing the thermal conduction capability of the PCB. The approach involves introducing multiple via holes filled with copper paste and make multi-layer boards to improve heat dissipation. To verify the effectiveness of this method, two PCB prototypes were fabricated: a six-layer board and an eight-layer board, both with identical thickness but different stack-up designs.

The final PCB layout is shown in Figure 2B. The left side contains four voltage sources providing chip bias supply and bootstrap voltages, while the right side constitutes the main power conversion stage. After the first stage, the output current is split into two interleaved branches in the second stage, and then recombined at the output. Figures 2C,D present the stack-up structures of the six-layer and eight-layer PCBs, respectively. Both prototypes adopt a 2–3 order stack-up with an overall thickness of 1.6 mm. To further withstand the high current stress under high-power operation, the vias are reinforced with copper paste filling, reducing thermal and electrical resistance.

3 Numerical calculation and simulation analysis

3.1 Numerical calculation

3.1.1 Selection of C m i d

C m i d serves to decouple the first and second stages, resolving inter-stage mismatch issues. For instance, in the two-stage two-phase circuit shown in Figure 1A, only a small number of capacitors are required to achieve inter-stage voltage stabilization.

Under ideal conditions, C m i d can be considered non-participating in the resonance processes of other passive components. Consequently, the inductor current and capacitor current exhibit a matched state. In this circuit, L 21 = L 22 = L 2, C 21 = C 22 = C 2. List the formulas:

f m i d = 1 2 π L 1 L 2 L 1 + L 2 C m i d C 1 + C 2 C m i d + C 1 + C 2

f r = 1 2 π L 1 L 2 L 1 + L 2 C 1 + C 2

Based on the equations:

f m i d f r = 1 + C 1 + C 2 C m i d

To avoid high voltage and current ripple at C m i d, it is recommended that the following ratio be designed within the specified range. f s w is the switching frequency, so the reasonable range for C m i d can be calculated by flying capacitor.

2.5 < f m i d f s w < 4

3.1.2 Loss analysis

Conduction Loss: Power dissipation generated when current flows through the on-resistance present in a MOSFET during the on-state:where R o n is the on-resistance of the MOSFET.

P o n = I o u t 2 ∗ R o n

Switching Loss: Losses incurred during the turn-on and turn-off transitions of the MOSFET:where t is the switching loss duration.

P s = V D S ∗ I D ∗ t ∗ f s w

Drive Loss: Losses generated by the circuitry driving the MOSFET.where Q t o l is the total charge required for driving.

P d = V g s ∗ Q t o l ∗ f s w

Component Loss: Losses introduced by other components besides the switching device, such as capacitors and inductors, during operation. Examples include conduction losses due to the Direct Current Resistance (DCR) of inductors and the Equivalent Series Resistance (ESR) of capacitors.

3.2 Simulation analysis

Using ANSYS Q3D simulation software, the validity of the extractor simulations was ensured through a carefully defined setup. The simulation region was bounded by a sufficiently large air box, with an “Infinite Sphere” boundary condition applied to accurately model the open-field environment. An adaptive mesh refinement process was employed, which iterated until the energy change between successive passes was less than 1%, guaranteeing solution convergence. The final mesh was characterized by a maximum element length of λ/10 at the frequency of interest to adequately resolve electromagnetic fields. Furthermore, the material properties were explicitly defined, assigning a standard FR-4 model to the PCB substrate and specifying copper with a characterized surface roughness model for the conductors. The circuit shown in Figure 3A was analyzed, and the PCB resistance distribution is illustrated in Figure 3B. V i n represents the resistance of the input voltage path, V o u t corresponds to the resistance of the output voltage path, Node indicates the internal resistance of the cascaded resonant switched-capacitor circuit, and PVSS refers to the remaining resistance. The results show that the resistances of V i n and V o u t are relatively low, suggesting limited conduction loss along the input and output transmission paths. In contrast, PVSS and Node contribute a larger portion of resistance loss, implying that these areas impose greater current transmission impedances and are likely to generate higher energy losses. Therefore, additional attention must be paid to the layout and routing of these regions during PCB design.

Figures 3C,D present the loss breakdown for the six-layer and eight-layer boards, respectively. The results reveal that the eight-layer PCB exhibits a lower proportion of related losses compared to the six-layer counterpart. This improvement is attributed to the more favorable routing, via design, and copper plane distribution of the eight-layer PCB, which reduces current conduction loss within the board. Meanwhile, other loss components, including switching loss, inductor loss, driver loss, and device-related losses—remain nearly unchanged, as they are primarily determined by the converter topology, which is identical in both cases. Consequently, the reduction in PCB conduction loss directly decreases the total power loss and improves the overall efficiency. These results validate the effectiveness of PCB structural optimization in enhancing circuit performance.

4 Experimental results

During thermal testing, a standard 8025 DC fan was positioned approximately 10 cm away from the PCB, delivering an airflow velocity of 3.6 m/s (equivalent to approximately 110 CFM). This configuration was maintained consistently throughout all experiments to ensure the comparability and reproducibility of the thermal performance data.

By applying the PWM driving scheme shown in Figure 1, all MOSFETs achieve ZVS. The measured current waveforms at the operating switching frequency are shown in Figure 4A, exhibiting smooth and continuous half-sinusoidal profiles. This ensures that MOSFETs switch when the current is at or near zero, minimizing switching losses.

Figure 4B presents the efficiency curves of both PCB prototypes under a 48 V input across varying load currents. At light loads, conduction loss is negligible, and efficiency increases with current. At heavy loads, however, conduction loss, which scales quadratically with current, becomes dominant and reduces efficiency. The eight-layer PCB consistently outperforms the six-layer PCB at the same current, achieving a peak efficiency of 98.8%, in agreement with theoretical analysis.

Thermal performance was evaluated using infrared thermography, as shown in Figures 4C,D. Under fan cooling only, the six-layer PCB reached a maximum temperature of 84.3 °C, significantly higher than the 73.7 °C observed for the eight-layer PCB. These results indicate that the eight-layer PCB provides improved heat dissipation, leading to higher efficiency and reduced thermal stress. The thermal results further demonstrate that the eight-layer PCB has sufficient thermal margin to withstand higher current stresses during operation.

To quantitatively evaluate the contribution of the eight-layer PCB stack-up to efficiency improvement, a comparative analysis of the DC resistance (R d c) of the critical high-current paths is presented. Based on the formulawhere ρ is the resistivity of copper, l is the total current path length, w is the trace width, and t is the copper thickness, the primary power path in the six-layer design was distributed across two layers, each with 2 oz copper thickness. The calculated total R d c for this path was approximately 0.45 mΩ. In the upgraded eight-layer board, the stack-up laminates adjacent 2 oz copper layers, effectively doubling the copper thickness to 4 oz for key power layers. Furthermore, the optimized layout reduced the current path length l by about 15%. Considering both the increased thickness and shortened path, the calculated R d c for the critical path in the eight-layer board is reduced to approximately 0.28 mΩ. Under a full load of 70 A, the conduction loss solely from the PCB traces decreases from about 2.2 W for the six-layer board to about 1.37 W for the eight-layer board, a reduction of approximately 0.83 W. The remaining efficiency gain (totaling approximately 1.5%) primarily stems from the enhanced thermal performance, which lowers the junction temperature of the semiconductor devices and thereby significantly reduces their conduction losses.

R d c = ρ · l / w · t

To ensure compliance with electromagnetic immunity standards such as IEC 61000-4-34 and to guarantee reliable operation in data center environments, the dynamic load stability of the proposed converter was rigorously evaluated. A load transient test was performed where the load current was switched between 25% and 100% of the rated value with a slew rate of 50 A/μs. The output voltage exhibits a maximum deviation of ±30 mV, which is well within the typical ±5% tolerance band for advanced microprocessors. The voltage recovers to within ±1% of the nominal value within 10 μs. This robust performance is attributed to the optimized wide-bandwidth control loop and the low-ESR output capacitor network, which collectively ensure a low output impedance over a wide frequency range, effectively suppressing voltage spikes caused by rapid load changes.

5 Conclusion

This study demonstrates the design of a high-power 48 V-to-12 V DC–DC converter based on resonant switching and ZCS technology. The prototype achieves 96.1% full-load efficiency at 70 A and 98.8% peak efficiency. By optimizing PCB stack-up and via structures, system efficiency is improved by 1.5% and the temperature rise of critical components is reduced by 9.6 °C. Experimental validation confirms that the proposed converter maintains stable electrical performance and thermal reliability across a wide load range, fulfilling the stringent requirements of data center applications for high efficiency and high power density.

This work provides a practical system-level optimization strategy to address the thermal management and efficiency bottlenecks of high-power converters, with clear potential for engineering application. Future research will explore the integration of planar magnetics, the adoption of GaN devices, and the implementation of intelligent control algorithms to further advance power systems toward higher density and smarter operation. It will also integrate multi-objective thermal optimization methodologies proven effective across microchannel heat sinks (Wang et al., 2020) and transient pulsed cooling strategies (Meng et al., 2020; Meng et al., 2021; Wang et al., 2021), rather than relying on discrete prototype comparisons. Adaptive reinforcement learning approaches for dynamic energy resource coordination (Wu et al., 2024) could enable real-time thermal-electrical co-optimization in multi-phase systems. Such advances are increasingly urgent as rising global temperatures threaten power electronics reliability (Wu et al., 2026a), though targeted device-level improvements can partially offset these climate-driven challenges (Wu et al., 2026b). Integration of planar magnetics, adoption of GaN devices, and implementation of intelligent control algorithms to further advance power systems toward higher density and smarter operation.

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Footnotes

Edited by: Mari Prasath, KSRM College of Engineering, India

Reviewed by: Lalith Pankaj Raj Nadimuthu, Gandhigram Rural Institute, India

Syed Owais Athar, University of Nebraska-Lincoln, United States