Adiabatic capacitive neuron: an energy-efficient functional unit for artificial neural networks

1 Introduction

Adiabatic Logic (AL) is a charge recovery design technique that operates with a gradually alternating AC power supply that periodically returns capacitive charge to the supply (Teichmann, 2012). This significantly differs from traditional, non-adiabatic, CMOS solutions that use a fixed DC supply. Appreciating the complexities of designing an energy-efficient AC power supply (Raghav et al., 2017; Jeanniot et al., 2017; Raghav et al., 2016; Maksimovic et al., 2000), previous AL work has successfully demonstrated the potential for significant energy savings (Blotti and Saletti, 2004; Oklobdzija et al., 1997; Raghav and Bartlett, 2020; Tang and Liter, 2010; Maheshwari and Kale, 2019; Houri et al., 2015; Maheshwari et al., 2018). It has been actively researched, including the novel implementation of an adiabatic hardware description language model, which shows timing agreement with transistor-level simulations (Maheshwari et al., 2021a). Additionally, it has been integrated with other low-power techniques and emerging devices (Kahleifeh et al., 2023), as well as an adiabatic leaky integrate and fire neuron featuring a refractory period and ultra-low energy operation Massarotto et al. (2024). As such, AL techniques are ideal for the implementation of power-hungry Artificial Neural Networks (ANNs). This includes capacitive ANN solutions (Maheshwari et al., 2021b; Ozdemir et al., 1996; Padure et al., 1999) and, most recently, with emerging memcapacitor configurable devices (Demasius et al., 2021). The simplest mathematical model of an artificial neuron is comprised of a vector dot-product between a number of input signals and a corresponding set of weights (or synapses) Botros and Abdul-Aziz (1993) followed by a non-linear activation function Lippmann (1987). The neuron output can then act as an input to other ANs in a multi-layer, multi-AN network. In digital hardware, this translates to large numbers of power-hungry multiply-accumulate operations. Optimizing artificial neurons and synapses for energy is, therefore, a key target for building efficient artificial intelligence systems.

Substantial work has been done on the implementation of synapses in hardware using devices such as resistors, MOSFETs, sink or source DC currents, and capacitors (Teng, 2006; Çilingiroǧlu, 1991; Verleysen et al., 1989; Pelayo et al., 2005). Out of these, capacitive solutions are the most desirable because of their flexibility in fabrication technology, simple sensing, reduced sensitivity to process variations compared to active devices and high energy efficiency. Over the years, many Switched-Capacitor (SC) neural networks have been proposed to perform computations, such as the analog dot product, instead of using traditional digital methods (Bankman and Murmann, 2017; Tang et al., 2022). The earliest implementation demonstrated energy efficiency at the expense of increased complexity (Tsividis and Anastassiou, 1987). Another work presented a fully synchronous SC-based self-organizing analog neural network with a winner-take-all circuit, capable of computing the AN dot product (Maundy and El-Masry, 1991). Further SC implementations include a differential comparator-based charge redistribution design with symmetric capacitor banks on either side (López-García et al., 2004). This configuration offers better stability but dissipates energy by transferring charge from the supply to ground during each reset. Capacitor leakage over time further degrades functionality and increases energy consumption. Using a sinusoidal AC supply with energy recovery via charge transfer could potentially mitigate leakage losses.

In parallel with SC and AL developments, there has also been significant recent research into Binary Neural Networks (BNNs) that use neurons with binary inputs and activation functions (Qin et al., 2020). Work in this area has been driven by the desire for fast and low-resource (memory) AN implementations in digital hardware (Yayla et al., 2023). Consequently, BNNs are trained with binary, ternary, or heavily quantized, positive and negative-valued weights for optimal storage and efficient computation. Researchers have shown that BNNs with more neurons can match the classification performance of state-of-the-art ReLU-based ANNs on datasets like MNIST and CIFAR-10 (Hubara et al., 2018). Novel AL-based SC hardware with binary I/O neurons is therefore well-suited for BNNs.

The primary goal of this work is to introduce a complete and highly energy-efficient, analog, fixed (or baked-in) hardware implementation of an, well-suited for energy-intensive feature extraction ANN front-ends, such as those used in transfer learning (Weiss et al., 2016). As a secondary aim, we refine and extend the Adiabatic Capacitive Artificial Neuron (ACAN) architecture presented in the authors’ prior work (Maheshwari et al., 2022). While the earlier study provided a detailed and practical analysis, it did not consider the accurate circuit-level mapping of real-world artificial neurons. In this next-generation design, as illustrated in Figure 1, functional support for both real-valued positive and negative weights is introduced, susceptibility to variations in the adiabatic power clock is significantly reduced and the accuracy of the binary threshold logic is improved via a new low-offset TL circuit. Nonetheless, prior work on switched-capacitor (SC) neural networks—starting with the seminal work of (Tsividis and Anastassiou, 1987)—relied on proportional mapping schemes to convert artificial-neuron weights into capacitance values. Later efforts examined dot-product computation in non-adiabatic SC networks by explicitly relating stored charge to synaptic weights and capacitor sizing Maundy and El-Masry (1991). In contrast, the present ACN approach enables energy-efficient adiabatic operation while preserving accurate neuron-level mapping. Finally, the paper discusses the benefits of the highly scalable properties of the new design and compares it with a purely CMOS-based equivalent solution. Through comparative analysis and post-layout based validation, this work aims to demonstrate how the adiabatic technique can enhance energy efficiency by robustly mapping real-valued AN weights to ACN circuits to generate equivalent functionality.

2 Adiabatic capacitive neuron: Design overview

An artificial neuron comprises a set of weights (synapses) and an activation function. This paper considers an artificial neuron with a Heaviside activation function that has N binary inputs, x i where i is an element of the indexing set I = { 0 . N − 1 }, and has a single binary output, y. The output is expressed aswhere w i are N trained weight values and τ is a constant bias value. The weights N may be real-valued or quantized and can be split into two disjoint sets of N + positive-valued (excitatory) weights, w i + where i ∈ I +, and N − negative-valued (inhibitory) weights, w i − where i ∈ I −. I ± are disjoint indexing subsets of I such that N = N + + N −.

y = 1 , if ∑ i ∈ I w i x i ≥ τ 0 , otherwise (1)

Figure 1 introduces a Double-Tree Single-Clock (DTSC) implementation of an ACN comprising two capacitive trees and a single sinusoidal Power Clock (PC). It includes a minimal set of N synapse capacitors required to embody the AN weights. This includes a subset of N + synapse capacitors, C i +, in the first (positive) capacitive tree. The capacitance values of each C i + map from the set of N + positive-valued AN weights, w i +, defined in Equation 1. It also has N − synapse capacitors, C i −, in the second (negative) capacitive tree with capacitance values mapped from the magnitude of each negative-valued AN weight, w i −.

A set of N Single-Pole Double-Throw (SPDT) switches is associated with each of the N synapse capacitors in the two capacitive trees. Each switch acts as a charge-steering element, synchronized with the slowly varying power-clock that connects to a synapse capacitor C i bottom plate. When the switch connected to x i is active, the rising and falling phases of the PC cause the corresponding node voltages to track the supply ramps smoothly, enabling near-adiabatic energy transfer. If the switch is inactive, then the corresponding C i bottom plate is grounded. The modulation of the inputs combined with their synapse capacitances generates two sinusoidal membrane voltages, v m ±, at the input terminals of the threshold logic. The TL, which implements the AN activation function, then generates the final output, y, based on the two input membrane voltage values. If v m + > v m − at the time of sampling, the comparator outputs a binary value of 1, otherwise, 0. The result is a hardware implementation of AN defined in Equation 1, with the switched capacitors allowing for energy-efficient, adiabatic operation.

The ACN also includes bias capacitors ( C b ± ) to support the software bias term, τ, ballast capacitors ( C d ± ) and DC bias voltages ( V B ± ) connected via a Transmission Gate (TG) switch to the positive and negative terminals of the comparator. The C b ± and C d ± capacitors are important as they control the swing amplitude of v m ± at the comparator inputs. The maximum number of necessary capacitors in an N-input ACN is N + 4. Note, under certain conditions, the bias and/or ballast capacitors can be omitted.

2.1 Adiabatic capacitive tree network

A single SPDT-capacitive synapse with a TG reset/bias switch for v m, along with bias and ballast capacitors, is depicted in Figure 2a. Figure 2b shows the transistor-level diagram of a single capacitive synapse with a ballast capacitor; V B is omitted for clarity. The PC is instrumental in the working of the capacitive tree. The time-varying sinusoidal PC signal voltage, V p c ( t ), varies from rail-to-rail, to enable computation and charge recovery. It operates in two modes, namely,: R e s e t M o d e and O p e r a t i o n a l M o d e. In R e s e t M o d e, the system is in an idle state, where the PC is resting at its minimum level. The O p e r a t i o n a l M o d e features a sinusoidal, wave-like behaviour and is divided into two phases. During the upswing (rising) of each PC voltage wave, the system is in the E v a l u a t i o n P h a s e and charge enters through the SPDT switches onto the synapse capacitors. Conversely, during the downswing (falling) of the PC wave, the system enters the R e c o v e r y P h a s e and charge recedes from the synapse capacitors via SPDT switches back to the specially designed Power Clock Generator (PCG) (Maheshwari et al., 2022), allowing near-adiabatic energy exchange. The different modes and phases are illustrated in Figure 2c. The parasitic capacitances associated with SPDT synapse switches primarily impact overall energy consumption through additional charge and discharge events, while having a negligible effect on the v m ± node voltage due to their isolation from the charge-integration path (Maheshwari et al., 2022).

The single-pole single-throw, TG switch in Figure 2a is connected to a constant bias voltage, V B, and is on (closed) in R e s e t M o d e. The membrane voltage v m consequently takes on the value of V B at this time, providing a stable initial, minimum v m throughout the entire cycle. When computation begins, the TG switch opens and v m depends on the state of the synapse switch and capacitance. When the input is zero ( x i = 0 ), the switch is connected to ground via transistor M 3 (see Figure 2b) and appears parallel to the ballast capacitor, effectively summing together as C i + C d at v m. When the input, x i = 1, the synapse capacitor is connected to the PC via transistors M 1 and M 2. During E v a l u a t i o n P h a s e, the synapse and bias capacitor forming a divider with C d and parasitic capacitance to ground at the v m node starts charging. The parasitic capacitances at the v m node originate primarily from the top plate parasitic capacitance of C i and the input transistors of the TL stage. To simplify the analysis and maintain clarity in the modeling, these parasitic contributions are explicitly lumped post-mapping into a single ballast capacitance term, C d, in the equations presented below.

Considering the general case, with N synapses distributed across two capacitive trees, the comparator membrane voltages, v m ±, at time t, can be determined by standard capacitive voltage division aswhere the denominator terms C A ± = C T ± + C b ± + C d ± represents the total capacitance in each tree and C T ± = ∑ i ∈ I ± C i ± are the total synapse capacitances per tree. The mathematical proof for the above equation is elaborately given in (Smart et al., 2025). The use of SPDT synapse switches, compared to the TG synapse switches used in ACAN, means that C A ± is constant and independent of the input x i. There is now a linear relationship between v m and x i, similar to that defined by the software AN condition in Equation 1. The membrane voltages can also be expressed as shown in Equation 3 where C o n ± is the sum of the switched on capacitor values ( x i = 1 ) plus the bias capacitor C b ±, and C off ± is the sum of all the switched off capacitors ( x i = 0 ) connected to ground, plus the ballast capacitor, C d ±.

v m ± t = V B ± + V p c t ∑ i ∈ I ± C i ± x i C A ± + C b ± C A ± (2)

v m ± t = V B ± + V p c t C o n ± C o n ± + C off ± (3)

A proportional mapping scheme can be applied to convert the abstract software AN weights to physical ACN capacitance values, as originally proposed in (Tsividis and Anastassiou, 1987), for functional equivalence, as defined bywhere w T = ∑ i | w i | and C T = C T + + C T −. The value of C T can be considered a design choice that controls the total physical area of the ACN. The software bias, τ, can be mapped in the same way onto one of the bias capacitors, depending on the sign. It should be noted that there is a requirement to train the AN weights and select a value of C T such that the minimum C i is greater than, or equal to, the minimum supported by the technology, C min. The design choice of C T, and properties related to the mapping strategies are presented in (Smart et al., 2025).

C i ± = | w i | C T w T (4)

The fixed capacitor values control the swings of the membrane voltages during each PC waveform, C i ±, representing the AN weights, and the inputs, x i. As such, the extent of the swing range at the peak of the wave lies between the two conditions when all inputs are logic ‘0’ and when all inputs are logic ‘1’, as expressed in Equation 5

v m ± t = V B ± + V p c t C b ± / C A ± , ∀ x i = 0 V B ± + V p c t C T ± + C b ± / C A ± , ∀ x i = 1 (5)

On the other hand, ACAN (Maheshwari et al., 2022) requires a suitably large-valued ballast capacitor as a mandatory requirement. However, in ACN, some ballast capacitance is naturally provided from SPDT-grounded synapse capacitors. The two ballast capacitors, C d ±, are typically still required and, importantly, act as asymmetric scaling terms to balance the two capacitive trees. This novel balancing functionality allows for the mapping of N software weights to a minimal set of N capacitors, whilst providing identical functionality compared to the software AN, as defined by Equation 1. The derivation of the specific capacitance values of C b ± and C d ±, which are required to complete this mapping, is discussed in detail in (Smart et al., 2025).

2.2 Threshold logic

The Threshold Logic (TL) unit in the DTSC ACN implements the neuron’s activation function. The two membrane voltages generated by the capacitive tree network in Section 2.1 serve as inputs to the TL circuitry. The improved TL design, introduced in this paper, includes two stages as depicted in Figure 3. The first stage is a Dynamic Latch Clocked Comparator (DLCC), and the second stage is a proposed Clocked Set-Reset (CSR) latch. A pMOS variant is preferred over an nMOS variant, as it eliminates the need for external biasing to keep the membrane potential above the subthreshold region, thereby reducing energy consumption. The complementary clock C L K b, for the proposed clocked SR latch, is derived internally by inverting the external C L K signal. More conventional designs, such as the one from (Matsui et al., 1994), which we use to benchmark against, use a NAND/NOR-based SR instead of the CSR latch (see Supplementary Figure S1). Conventional TL design suffers from two major issues (Matsui et al., 1994), namely, 1) large propagation delay, affecting the offset voltage, and 2) latching the wrong data with reduced voltage headroom.

With reference to Figure 3a, during the pre-charge phase, the clock signal ( C L K ) transits from zero to V D D. Consequently, M 9 is turned off and M 1, M 4, M 11 and M 12 are turned on. As a consequence, the output nodes (Q R and Q S) of the DLCC are pre-charged to zero and the DC path from the supply to the ground is cut off. As such, a second stage is necessary to latch the output correctly. During the pre-charge phase, the second stage C L K b signal transits from V D D to zero and the transistors L 9 & L 10 and L 5 & L 6 are switched off, thus the CSR latch holds the previous state of Q and Q b, giving a stable output for each clock period.

Next, in the comparison phase, the C L K signal transitions from V D D to zero, and the transistors M 1, M 4, M 11, and M 12 are turned off, while the M 9 transistor is switched on. The DLCC starts by comparing the two input voltages: v m − and v m +, resulting in the output to swing differentially, causing one output node to move to V D D, and the other complementary output node to ground. Assuming v m + > v m −, the output Q S is pulled to V D D and due to the positive feedback transistors, Q R is pulled down to 0 V. The output from the first stage is fed as input to the CSR latch. Here, Q S is connected to the set S terminal and Q R to the reset R terminal. As a result, transistor L 6 starts conducting, whereas L 5 is switched off. Since the transistors L 9 & L 10 are already on, the output node Q b discharges to ground and due to the positive feedback, the node Q charges to V D D. The layout plays an important role in the offset voltage and resolution. To keep the TL offset as low as possible, the layout is drawn symmetrically and is shown in Figure 3b. The Supplementary Section 1 reports a comparison between the conventional and proposed TL, and the waveform is shown in Supplementary Figure S2.

The post-layout rising/falling offsets and energy consumption are evaluated across three process corners and temperatures from − 5 5 oC to 12 5 oC. The testbench setup, shown in Supplementary Figure S3, with a C L K frequency of 1M H z and an input voltage range V i n of −0.1V to +0.1V with a common mode voltage V c m = 0.8V, giving the input resolution of 1 m V / μ s. Based on Tables 1, 2, the conventional TL shows a large asymmetry in the offsets. It has a large rising post-layout offset of 10 s of m V, ranging from 27m V at 12 5 oC FF corner to 13m V at − 5 5 oC SS corner, while the proposed TL has a range from 9m V to 5m V for the same corners and temperature. On the other hand, the conventional TL shows a lower falling offset ranging from 5m V at 12 5 oC FF corner to −1m V at − 5 5 oC SS corner, while the proposed TL ranges from 3m V to 9m V. Overall, the proposed TL shows greater offset symmetry and consistency. On the other hand, the simulated energy across corners and temperatures is shown in Supplementary Figure S4, with the proposed TL reducing the average energy by 1.5% (SS) and 2.3% (FF) vs. the conventional design.

TABLE 1. Post-layout rising offset voltage ( m V ) of the conventional ( C o n v ) and the proposed ( P r o p ) TL design across process corners, and temperatures.

TABLE 2. Post-layout falling offset voltage ( m V ) of the C o n v and ( P r o p ) TL design across process corners, and temperatures.

Finally, the TL typically samples the membrane voltages at the peak of the PC clock when V p c ( t ) = V max, at the end of Evaluation Phase. Combining this information with Equation 2, the TL will produce output-high under the condition shown in Equation 6 and output-low otherwise:

V B + + V max ∑ i ∈ I + C i + x i + C b + C A + ≥ V B − + V max ∑ i ∈ I − C i − x i + C b − C A − (6)

As discussed in the previous section, the ballast capacitance values, C d ±, in C A ± can be used to scale one or both sides of the condition in Equation 6. This scaling can be used to ensure that the swing range of the membrane voltages v m ± is always within the operational voltage range of the comparator [0, V cut], where V cut may be significantly lower than V max. V cut is approximately V D D − | V thp |, where V thp is the threshold voltage of the pMOS transistors used in the comparator. Importantly, owing to the differential design of the ACN, the sampling timing does not need to be highly precise. While sampling ideally should occur at the peak, v m peak, the system can tolerate reasonable timing skew with only a modest reduction in v m peak, with potential classification errors arising only under extreme timing mismatches. A Supplementary Figure S5 demonstrates that our DTSC network can tolerate dynamic sampling of the differential voltages, v m ±, thus meeting timing closure of the TL. The post-layout transient simulations are shown for two representative test vectors, TV4 and TV12, selected to capture worst-case loading and near-threshold decision conditions. Additionally, the proposed architecture is not restricted to real-valued weights and can readily accommodate quantized as well as binary synaptic weights (+ 1/− 1) (Smart et al., 2025; Yayla et al., 2023).

3 Hardware implementation of ACN

The hardware implementation of a single neuron with 12 1-bit input synapses, ACN, is done in Cadence EDA tool using a 0.18 μ m commercially available CMOS technology at a nominal V D D = 1.8 V supply and 1M H z operating frequency. The PC is generated using the PCG discussed in Supplementary Section 3, while a detailed analysis is provided in (Maheshwari et al., 2022; Raghav et al., 2025). All SPDT synapse switches are kept at a technology minimum width. Synapse capacitors are implemented using MIMCAPs, whose values are chosen based on the mapping Equation 4, and quantized to allowable MIMCAP widths and lengths. Bias and ballast capacitance values are selected using the optimal conditional mapping process defined in Smart et al. (2025). Table 3 shows the mapped configuration for a single ACN, generated using weights extracted from a randomly selected software AN with a fixed τ = 0.1, that includes a selection of both positive and negative weights as well as varying weight magnitudes. The ACN configuration uses: V max = 1.8 V, V B ± = 0 V, C min = 35 f F and V cut = 1.3 V. The total capacitance of this ACN is 3907 f F with a total synapse capacitance, C T = 2115 f F.

TABLE 3. DTSC N = 12 ACN configuration with N + = 5, I + = { 0,5,6,9,10 } and N − = 7, I − = { 1,2,3,4,7,8,11 } where i is the synapse index, w i the abstract weight and C i the corresponding synaptic capacitance.

Using the parameters defined in Table 3, the capacitive synapse trees are instantiated in the design and integrated with the TL gate to complete the computation based on the input signals, x i. Although not optimal, both stages of the TL were designed using minimum-size transistors for minimum energy consumption. The physical layout of the circuit with RC extraction was performed before simulating the circuit for hardware and software comparison. The post-layout extracted result shows an extra parasitic capacitance of approximately 30 f F value on each of the v m ± nodes, acting parallel to the C d ±. Therefore, these parasitic values can be compensated for within the ballast capacitance values during fine-tuning. The ACN circuit diagram and its layout are shown in Figure 4. Each capacitor, having equal length and width, is oriented in an array format for uniform connectivity and area. The SPDT synapse switches are on the extreme left side of the layout, which will be connected to the 12 1-bit inputs and the PC. The TL gate is on the right side of the layout, next to the negative ballast capacitor. Large antenna diodes (reverse diodes) having W / L = 10μm/10μm were used to reduce antenna effects during fabrication. The unoptimized dimension for our single neuron with 12 1-bit input synapses is 88.9 μ m × 50.9 μ m.

4 Results

To analyse ACN performance, a subset of test vectors from the original weight-training dataset was selected, along with a number of input corner cases, and is reported in the Supplementary Table S1. In total, 16 test vectors were chosen based on two factors: 1) predicted input differential voltage (v m d = v m + - v m −), to test the accuracy of the TL offset, and 2) minimum to maximum ACN energy dissipation levels based on the computed capacitive load of the PC. See Supplementary Section 4 for the derivation of the capacitive load.

Performance evaluation is based on the full custom post-layout for all the designs using the Spectre simulator. The PCG circuit parameters defined in a previous paper Maheshwari et al. (2022) are used in this work and are set as follows: bypass-switch on period, t O N = 60 n s; power supply capacitance, C E = 25 p F and inductance, L P C = 1 m H, that generates a nominal power clock frequency of 1 M H z. An additional ideal capacitive load of 100 f F is attached to the output of the TL gate throughout the post-layout simulation. The working and generation of the P C signal can be found in the Supplementary Section 3.

4.1 Functionality

To verify functionality, the ACN output obtained with the improved TL design is compared with that of the conventional TL-based ACN and the theoretical adiabatic model. For each input test vector, the theoretical model predicts the peak membrane voltages, when V p c ( t ) = V max, based on Equation 2, and the TL output based on condition in Equation 6. Table 4 compares the theoretical model against Cadence post-layout hardware simulations. It is also worth reporting that the theoretical ACN model output defined by Equation 2 has been verified to match that of the software ANN as defined in Equation 1.

TABLE 4. Comparison between the theoretical model, proposed ACN and ACN using conventional TL design. The red highlight box in the table indicates discrepancies between theoretical and circuit outputs.

The two hardware-generated ACN membrane voltages (proposed and conventional) are in accord with one another, having a few m V differences in the two v m ±. As TL should not affect v m ±, these differences are attributed to measurement variations arising from the v m ± peak voltage sampling time. Both hardware designs have an average absolute error of 14m V between the measured membrane voltages and that predicted by the theoretical model, with a maximum of 43m V for the proposed TL and 44m V for the conventional TL.

The test vectors (TV) (see Supplementary Table S1) are selected to test the system in a wide range of v m d derived from different input patterns, to identify the loss of functionality and the minimum to maximum energy dissipation. The membrane voltages and the outputs for the 16 TV’s are shown in Table 4. The conventional TL uses a combinational NOR-based SR latch which has an asymmetric gate switching threshold for low-to-high and high-to-low transitions. The NOR SR latch introduces an undefined switching threshold, causing the final output to latch at a different time. The final SR logic decision no longer corresponds strictly to the comparator threshold, degrading analytical accuracy and predictability. This can be seen in Table 1, which corresponds to a higher offset compared to Table 2. As a result, shown in Table 4, the ACN design with a conventional TL has a much larger v m d between 16.8m V to 48.1m V, resulting in a high number of functionality failures. In contrast, the proposed TL implementation employs a clocked SR latch that enforces a well-defined dynamic comparison window and preserves decision fidelity through controlled regeneration. Thus, improving the offset across process and temperature corners, which is shown in Tables 1, 2. Moreover, by synchronizing the comparison phase with clock-controlled input transistors, the proposed design suppresses premature regeneration and reduces the dominance of device mismatch during near-threshold operation. This results in a substantially lower rising offset, enabling reliable logic-1 generation for differential input voltages as small as v m d ≥ 6.3m V.

4.2 Energy consumption

The total energy dissipation of an ACN consists of three components: 1) energy broadly due to the finite on-resistance of the bypass nMOS switch in the PCG, E PCG - see Supplementary Figure S7; 2) losses due to adiabatic charging and discharging of the synapse capacitance, E A L Younis (1994); 3) TL consumption, E T L. The total energy dissipation E T in one cycle (excluding subthreshold leakage Chanda et al. (2015)) is given by:

E T = E PCG + E T L + E A L (7)

E PCG = 1 2 C P C V x 2 1 − e 2 − t O N R P C C P C (8)

E T L = C T L V D D 2 (9)

E A L = C L V D D 2 ⋅ π 2 8 ⋅ R syn C L T r (10)

The first term in Equation 7 denotes the energy consumed in the PCG when the internal bypass switch is activated. This lost energy, E PCG, is given by Equation 8, where C P C is the capacitance on the PC node, R P C is the ON resistance of the nMOS switch in PCG, V x is the residual voltage when the switch is on and, finally, t O N is the time when the PCG is in reset mode. The complete proof for the energy dissipation due to the sinusoidal ramp generator can be found in the foundation work of (Younis, 1994). The second term of E T is the TL energy loss, E T L, due to the comparator and the latch, and is given by Equation 9. The comparator will switch state at every clock cycle, while the latch switches only once per operation. This gives almost a constant energy similar to standard inverter energy dissipation per switching event. Here, C T L is the equivalent total capacitance on the output TL node. The third term, E A L, is an adiabatic loss for an equivalent RC network circuit under sinusoidal stimulation (Younis, 1994), which is given by Equation 10. Here, C L is the total capacitive load on the PC node due to the synapse. The resistance of the synapse switch is represented by R syn. If the input is ‘1′, then R syn is a small value; otherwise, it will be very large, thus preventing the propagation of the PC signal to v m. T r is the third parameter that defines the ramping time of the PC. The slower the system, the greater the energy efficiency. However, at some point, the leakage energy will start dominating (Teichmann, 2012).

In Equation 10, the E A L energy is shown to be proportional to C L 2. Given that C L will be a function of the input pattern, and therefore C o n, the maximum energy dissipation of E A L is likely to occur near m a x ( C L ). In Supplementary Section 4, it is shown that, assuming an SPDT switch with negligible resistance, C L on each capacitive tree is given by the C o n quadraticwhich holds for C L ± > 0 as C A ± ≥ C o n ± and gives m a x ( C L ) when C o n ± = C A ± / 2.

C L ± = − C o n ± C o n ± C A ± + C o n ± (11)

The total synapse energy per operation measured in post-layout simulation for the ACN and CCN implementations is provided in Table 5. The reported synapse energy per operation includes the contribution of the PCG. The TL energy is constant for both implementations and is thus not included in the results. The capacitive load on the PC are computed using Equation 11. The derivation of the capacitive loading of Equation 11 is discussed in Section 4 of the Supplementary document. The ACN network demonstrates average energy savings of more than 90% typically compared to the CCN. The data points corresponding to TV8 and TV5 deviate from this trend and can be considered outliers, likely arising from input capacitance loading conditions that differ from the nominal regime. However, the ACN energy reported in Table 5 does not include the CMOS inverter energy shown in Figure 2b. This non-adiabatic inverter circuit (powered by a DC voltage) would cause the total synapse energy dissipation to increase by ≈ 30–35%. It has been excluded here, as in multilayer networks, the complementary output from the previous layers’ threshold logic can be used directly instead. However, in the case of multilayer CCN, extra circuitry between layers is mandatory to provide transition (either zero to V D D or vice-versa), enabling the synapse capacitors to compute the membrane voltages. The description of the CCN design is presented in Supplementary Section 2 and the circuit diagram is shown in Supplementary Figure S6.

TABLE 5. The comparison of the total synapse energy/operation between the proposed 12-input ACN and CCN for 16 test vectors having different idealized capacitive loads. The table also demonstrates the percentage energy saving of the proposed ACN design compared to the CCN.

The capacitive load strongly influences both energy dissipation and recovery in an adiabatic system. While increasing capacitive load raises the total stored energy, it also increases the amount of charge returned to the PC, with dissipation remaining limited by the PC ramp time, T r as described by the adiabatic loss energy expression in Equation 10. For TV8, where all inputs are zero, the effective load capacitance C L is dominated by the bias capacitors ( C b ± ), resulting in limited charge recovery, while the energy dissipation is primarily set by the PCG. Consequently, for test vectors such as TV8 and TV5 with minimal active synapses, only marginal energy savings are achieved which is still very substantial, underscoring the importance of adiabatic charge recovery for energy efficiency.

The plot in Figure 5a represents the data from Table 5 with respect to the on-capacitance C o n. As predicted, the maximum measured synapse energy is around m a x ( C L ), rather than all 1’s ( T V 2 ) input pattern. This is different from ACAN (Maheshwari et al., 2021b; Maheshwari et al., 2022) where C L will increase monotonically with C o n. We further note that despite a nominal frequency of 1M H z, differences in the PC capacitive load induced by different test vectors mean that the actual frequency changes slightly for each row of Table 5. The Figure 5b reflects the relationship between operational frequency, capacitive load and synapse energy. The actual frequency ranges from 979k H z (TV4: maximum load) to 997k H z (TV8: all zero inputs), which is an approximately 2% variation off the nominal frequency.

4.3 Frequency scaling

This subsection presents the results for a broader range of scenarios, where the nominal frequency varies from our baseline scenario of 1 M H z. The added frequencies are: 100k H z, 500k H z, 10M H z and 100M H z. For all frequencies, some coarse-grain optimization is done in the balance between the capacitance and inductance of the PCG and is reported in Table 6. Due to the synapse loading on the PC, the actual operating frequency across the range drops by about 2 % vs. nominal (see Figure 5b). The total 12 1-bit input synapse energy per operation for ACN and CCN across operating frequency for 3 test vectors is reported in Figure 6. It can be clearly seen that with decreasing frequency (i.e., increasing ramping time ( T r ) and period ( t O N )), energy dissipation reduces. It is observed that at 100k H z, the system energy starts to increase, which mainly arises due to the PCG non-idealities (Raghav et al., 2025). We see ∼ 7.67 f J / M H z average change in energy for TV4 for the frequency range [0.5, 10]M H z, which shrinks to ∼ 4.76 f J / M H z within [1, 10]M H z. Significant energy savings of > 90% are clear within [0.5, 10]M H z.

TABLE 6. Power clock parameters at different frequencies at maximum loading (TV4: worst case synapse energy). The channel width of the nMOS ( M P C ) and C E in the PCG are constant and set to 10μ m and 25p F respectively.

4.4 Voltage scaling

In both adiabatic and non-adiabatic logic, the energy dissipation is directly proportional to the square of the power supply. Thus, a further energy reduction can be achieved if the supply voltage is reduced. In adiabatic logic, voltage scaling affects both non-adiabatic energy dissipation in the PCG, E PCG, and the adiabatic loss, E A L. In an adiabatic system, energy consumption can be reduced under voltage scaling by adjusting key parameters: lowering the ON resistance of the synapse transistor ( R syn ), increasing the resistance in the PCG ( R P C )—achieved by reducing the width of the nMOS switch in the PCG—and decreasing the supply voltage ( V D D ), which linearly influences the node voltage V x. The on-resistances, R syn and R P C are inversely proportional to ( V G S − V t h ). As the supply voltage decreases, the E A L tends to increase while E PCG tends to decrease. However, the increase in E A L is balanced by the square of the supply voltage and the capacitive load. On the other hand, on decreasing V D D, V x also decreases, thus the overall energy dissipation of the PCG decreases.

The impact of supply voltage scaling on synapse energy dissipation is shown in Figure 7. The main trends are that: a) TV8 (all-off) follows a relatively smooth drop in energy, similar to what we see in the CCN and b) TV4 and 13 (actively loaded system) show that overall voltage downscaling does lead to a drop in energy, with levels below 1.3 V showing faster drops than the CCN. At 1V, the energy of TV4 and TV13 starts to approach that of TV8, which indicates that E A L has almost decreased to zero. Supplementary Table S2 shows ACN energy savings vs. CCN under voltage scaling. The adiabatic circuit shows an average saving of ∼ 95 % for all the test vectors, except for TV8 (all 0’s). As no switching occurs in the synapse circuitry with TV8, the dissipated energy is only due to E PCG.

4.5 Statistical analysis

Standard Monte Carlo simulations consisting of 1,000 runs for the proposed ACN and CCN post-layout designs were tested based on the worst-case loading/energy input vector pattern, TV4. We considered the global process variations (wafer-to-wafer and run-to-run) and mismatch (non-uniformity across individual wafers) Fischer et al. (2005). The statistical analysis uses the Low Discrepancy Sequence (LDS) sampling method provided in the Cadence tool, which has a uniform sample space coverage. Figure 8a clearly shows a right-skewed energy distribution for the ACN. The distribution appears to have a long tail, meaning a large number of occurrences are far from the mean value. This implies that, under certain conditions, an unexpectedly large synapse energy may be generated.

Figure 8b is a quantile-quantile (or Q-Q) plot to verify that the ACN synapse energy Monte Carlo results in Figure 8a are indeed not normally distributed. A correlation coefficient of 0.89 and a very small p-value reject the hypothesis that the data is normally distributed. The same analysis is also carried out for the CCN design. The distribution in Figure 8c appears to be normally distributed, which is confirmed by its Q-Q plot shown in Figure 8d, where all the data points lie on the line. A correlation coefficient of 1 indicates linearity and confirms the data as normally distributed. The coefficient of variation (CV) is defined as the ratio of the standard deviation to the mean. As the data points are well spread out, the CV for the ACN is calculated as 12.55, whereas for CCN it is 4.85. It is inferred that the skewed energy distribution in an adiabatic system originates from the conditional and nonlinear nature of charge recovery, where small variations in device parameters, such as threshold voltage, or timing can asymmetrically degrade recovery efficiency. Because energy dissipation (see Equation 10) depends multiplicatively on effective resistance, R syn, capacitance, C L, and ramping time, T r, rare recovery failures produce high-energy outliers, resulting in an intrinsically skewed distribution.

5 Conclusion

In this paper, we have introduced a novel, differential, adiabatic, switched-capacitor artificial neuron combined with a new threshold logic design. In comparison to previous work, such as ACAN, new functionality has been added in the form of support for negative-valued ANN weights through the differential DTSC ACN architecture. This could potentially mean fewer neurons are required overall to implement an ANN to the same level of functional performance. This ACN design also introduced new functionality in the form of a two-stage TL latch design to implement a binary activation function.

In terms of accuracy, the paper has shown that weights from a real ANN model can be easily mapped to synapse capacitance values to perform the same operation. The post-layout simulations have provided a good correlation between a theoretical software model and post-layout results. The new TL design was also shown to reduce errors in the ACN output due to its reduced offset compared to the conventional TL design. The differential design introduces some additional robustness that was missing in the previous ACAN design. The ACAN circuit Maheshwari et al. (2022) was susceptible to errors if the PC voltage changed for any reason. This is because the ACAN uses a fixed absolute DC threshold voltage, which the TL compares against its single membrane potential. The ACN eliminates this limitation by using a differential tree topology, with any errors with V p c ( t ) affecting both trees in the same way and consequently not affecting the output. It also means that the ACAN non-zero DC threshold voltage does not need to be supplied to each neuron. Furthermore, we have explored some important design parameters of this new ACN design, such as PC voltage and nominal frequency that can be adjusted without altering the mapped capacitor configuration. Although the new TL design in this work shows robustness across process-voltage-temperature corners, its behavior can be influenced by input-referred offset voltage, noise, and finite gain, which introduces uncertainty around the decision boundary. Additionally, delay and metastability become critical in the TL comparator when operating at high speeds or with slowly varying input signals. The non-idealities, related to kickback noise and loading, constrain the achievable precision and reliability of threshold-based decision making in practical implementations. A comprehensive characterization and optimization of these effects/impact represent important and timely avenues for future investigation, and are expected to provide valuable insight for advancing high-precision and scalable threshold-logic implementations.

In terms of energy efficiency, the post-layout analysis of a single neuron with 12 input synapses shows significant savings between 90% and 95% compared to an equivalent non-adiabatic CCN implementation. Monte Carlo simulations over 1,000 samples resulted in a skewed synapse energy distribution for the ACN. However, the CCN design showed normally distributed synapse energies. The non-normal distribution of the ACN is a result of its energy dependency on the synapse switch resistance and ramping time/frequency. However, it should be noted that even the ACN samples in the long tail of the distribution still outperformed those from the CCN.

Overall, the ACN represents a significant step forward in practical, high-energy-efficient, and accurate ANN computation. This paper has focused on a fixed capacitor array implementation, but with the recent advancement in mem-impedance devices, memcapacitors seem to be an interesting choice for SC networks due to their tunable properties, and have already been deployed with parallel multiply-accumulate operations (Demasius et al., 2021), in integrate-and-fire neural networks (Pershin and Ventra, 2014) and AN synapse neuro-transistors (Wang et al., 2018).

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Supplementary material

The Supplementary Material for this article can be found online at: https://www.frontiersin.org/articles/10.3389/felec.2026.1743265/full#supplementary-material

Supplementary material Supplementary material at the source

Footnotes

Edited by: Peter A. Beerel, University of Southern California, United States

Reviewed by: Baibhab Chatterjee, University of Florida, United States

Mikail Yayla, Ruhr University Bochum, Germany