Memory circuit elements for hardware security: a review from memristors to memcapacitors and meminductors

1 Introduction

The assurance of digital security in an interconnected world relies, at its most fundamental level, on the unpredictability and uniqueness of certain physical processes that cannot be inferred by an adversary. Classical software-based approaches, such as pseudorandom number generators, deterministic key-derivation functions, or static device fingerprints, are inherently constrained by the reproducibility of their computational substrate and are increasingly threatened by machine-learning-assisted modelling attacks and the imminent arrival of quantum computing (Singh et al., 2026; Shirisha et al., 2026). These limitations have motivated growing interest in hardware security primitives, in particular true random number generators (TRNGs) and physical unclonable functions (PUFs), which derive their security properties directly from irreducible physical phenomena. TRNGs provide entropy and unpredictability as the basis for cryptographic key generation, while PUFs exploit device-specific physical variability to enable unforgeable identity and authentication. Both require physical mechanisms that simultaneously provide randomness, uniqueness, and resistance to inference: properties hard to guarantee when the hardware operates in a low-dimensional, fully observable state space.

In this context, circuit elements with memory (memristors, memcapacitors, and meminductors) hold a theoretically privileged position among candidate physical substrates. Introduced by Chua (1971) and generalized to reactive elements by Di Ventra et al. (2009), these devices share the fundamental property that their present electrical response cannot be fully determined without knowledge of their past excitation history. This history dependence translates into security-relevant properties: the partial inaccessibility of internal state variables provides a physical basis for unclonability (as exploited in PUFs), sensitivity to initial conditions and intrinsic switching stochasticity supports unpredictability (as required by TRNGs), and the high-dimensional chaotic dynamics of multi-element memory circuits enable sustained entropy generation resistant to data-driven inference. Table 1 summarizes the three mem-element families across constitutive variables, energy storage, experimental maturity, reliability, scalability, and demonstrated security applications, serving as a state-of-the-art reference.

TABLE 1. Comparative overview of passive circuit elements with memory and their relation to hardware security.

ϕ: time integral of the voltage (flux); q: time integral of the current (charge); σ: time integral of the charge; ρ: time integral of the flux.

While the memristor has attracted significant attention in this context (Lv et al., 2021), both as a solid-state device and as a component in hardware-security applications, many of the proposed approaches rely primarily on device-to-device variability, stochastic resistive switching, or relatively low-dimensional nonlinear behavior, which may exhibit limited resistance to modelling, prediction, and machine-learning-assisted inference, particularly under conditions where sufficient data can be acquired (Kraleva et al., 2023; Rührmair et al., 2010). By contrast, its reactive counterparts (the memcapacitor and the meminductor) have been comparatively neglected in the hardware-security literature. This coupling of memory with energy storage introduces multi-timescale interactions, higher effective dimensionality, and richer nonlinear dynamics, potentially enabling stronger intrinsic unpredictability, dynamic uniqueness, and resistance to inference. However, the lack of systematic studies, experimental implementations, and unified theoretical frameworks for memcapacitor- and meminductor-based systems remains a significant gap, whose resolution is essential to establish whether these devices can provide fundamentally stronger physical guarantees for hardware security.

This mini-review synthesizes the state of the art on memristor-based security primitives (Section 2) and critically assesses the emerging landscape of memcapacitor- and meminductor-based approaches (Section 3). Section 4 identifies key open research challenges, and Section 5 concludes with a forward-looking perspective on memory-driven nonlinear dynamics as a foundation for next-generation hardware security.

2 Memristors in hardware security: state of the art

The memristor is a passive two-terminal element whose memristance links flux and charge (R _*m* = dϕ/dq), so its instantaneous resistance depends on the integral of past current flow (Chua, 1971). This history dependence manifests as a pinched i–v hysteresis loop and underpins the security applications reviewed below. The corresponding principles for the memcapacitor and meminductor are given in Section 3.1, with all three summarized in Table 1.

2.1 Physical unclonable functions

PUFs exploit manufacturing-induced variability to generate device-specific challenge–response pairs that are hard to clone or predict (Pappu et al., 2002; Herder et al., 2014; Al-Meer and Al-Kuwari, 2023). The memristor is particularly well-suited to this purpose as its resistance state depends not only on the present bias but also on the entire excitation history, and its fabrication-induced variability, which originates from stochastic filament formation, interface roughness, or local dopant fluctuations, produces device-specific signatures that are difficult to replicate (Roldán et al., 2023). Memristor-based PUFs have been realized in a variety of material platforms, including HfO₂-based RRAM, phase-change materials (PCM), and graphene oxide or laser-induced graphene, demonstrating competitive uniqueness and reliability metrics (Zahoor et al., 2025; Ibrahim et al., 2022). However, classical delay-based and memristive PUFs share a common structural vulnerability: their responses can be modelled with high accuracy from relatively modest challenge–response datasets (Gassend et al., 2002). Standard Arbiter PUFs are broken by logistic regression with prediction accuracies exceeding 99% using as few as ∼2,000 CRPs; even XOR-augmented variants require only tens of thousands of CRPs (Kraleva et al., 2023; Rührmair et al., 2010). This susceptibility is structural: the underlying low-dimensional state space can be tracked and reproduced by an adversary with sufficient data, regardless of the inference technique employed.

2.2 True random number generators

TRNGs based on memristive devices harvest entropy from the stochastic nature of resistive switching events, specifically from the probabilistic nucleation and dissolution of conductive filaments (or from charge-trapping fluctuations in ferroelectric structures) under applied bias. Two principal operational regimes have been exploited: i) switching-time jitter, where the random delay between voltage application and state transition is digitized to extract random bits (Jiang et al., 2017; Woo et al., 2021; Pazos et al., 2023), and ii) cycle-to-cycle resistance-state variability harvesting, where the spread in programmed conductance values across successive switching events serves as an entropy source (Gao et al., 2022). Key figures of merit include throughput, min-entropy per bit, power consumption, and compliance with randomness test suites such as NIST SP 800–22 (Bassham et al., 2010). For instance, the integration of a hexagonal boron nitride memristor with a commercial microcontroller demonstrated robust generation passing all NIST statistical tests at low operating voltages (Pazos et al., 2023). Compared to thermal-noise or ring-oscillator generators, memristive TRNGs offer clear advantages in miniaturization and CMOS compatibility, though two persistent challenges remain: characterizing the entropy source under aging and cycling stress (Roldán et al., 2023), and the temperature dependence of filament stochasticity (Cai et al., 2025), which can introduce statistical bias at operating extremes and requires post-processing correction or adaptive biasing.

2.3 Chaotic circuits and entropy sources

Beyond their use as stochastic switching elements, memristors enable autonomous chaotic oscillators without additional nonlinear components, since the hysteretic nonlinearity of the device itself sustains complex attractor dynamics (Itoh and Chua, 2008). Memristive variants of the Chua circuit produce chaotic trajectories in a three-dimensional state space defined by terminal voltage, current, and the internal state variable x (Muthuswamy and Chua, 2010), with positive Lyapunov exponents providing a well-defined measure of the entropy generation rate (Yue et al., 2025). From a security standpoint, the critical property is not chaos alone, but its combination with the partial inaccessibility of x to external measurement. An adversary monitoring terminal voltage and current observes only a projected shadow of the full state trajectory, while x evolves in an unobservable dimension. This partial observability, compounded by exponential trajectory divergence, makes memristive chaotic circuits attractive as physical entropy sources. Their main limitation is that memristor-only topologies typically sustain a single positive Lyapunov exponent, constraining attractor dimensionality and the adversary’s prediction horizon. This limitation motivates the transition to multi-element memory circuits discussed in Section 3, where (Yuan and Li, 2019) and (Wang et al., 2023) demonstrated progressively richer hyperchaotic dynamics by combining the memristor with reactive memory elements.

3 Memcapacitors and meminductors: an underexplored frontier

3.1 Device definitions and distinguishing properties

The memcapacitor and the meminductor extend the mem-element family to reactive components. A voltage-controlled memcapacitor is formally defined by C _*m* = dσ/dϕ, where σ is the time integral of charge and ϕ is the flux (time integral of voltage), so that the constitutive relation involves the second integral of the current and the first integral of the voltage (Di Ventra et al., 2009; Radwan and Fouda, 2015). Analogously, the meminductor is defined in the ρ–q domain, where ρ is the time integral of flux and q the charge. Both devices exhibit pinched hysteresis loops in their respective characteristic planes (q–v for the memcapacitor and ϕ–i for the meminductor), confirming the memory nature of their response. Beyond this formal analogy with the memristor, a critical distinction exists: both devices combine memory with energy storage, so that their internal state can evolve through passive or weakly dissipative dynamics, with complexity arising without the sustained energy expenditure associated with resistive switching (Demasius et al., 2021). At the model level, state trajectories are not necessarily subject to thermal relaxation affecting memristive internal variables at zero bias, a property with potential implications for idle-state retention, pending experimental validation.

On the implementation side, solid-state memcapacitors remain relatively rare, with demonstrations based on charge-trapping layers, ferroelectric capacitors, and electrolyte-gated structures (Demasius et al., 2021; Dinavahi et al., 2023). Meminductive behavior in passive two-terminal elements has only very recently been reported experimentally (Dinavahi et al., 2023; Dinavahi and Rusty Harris, 2025). In the absence of commercially available devices, emulator circuits based on operational transconductance amplifiers and current conveyors provide a physically meaningful experimental methodology: they faithfully reproduce constitutive relations and circuit-level dynamics while differing from real devices in noise spectral density, thermal behavior, and scalability, all of which are directly security-relevant (Romero et al., 2021a; Romero et al., 2019; Romero et al., 2020; Romero et al., 2021b).

3.2 Isolated use in security contexts

Publications exploring memcapacitors or meminductors specifically in the context of hardware security remain scarce. Most existing works focus on demonstrating chaotic oscillations or multistable behavior without addressing dynamical properties from a security-motivated perspective (Akgul et al., 2020; Abro and Atangana, 2021; Romero et al., 2021b). This gap is not merely quantitative but conceptual: memcapacitors are treated as functionally interchangeable with memristors, with analysis grounded in the nonlinear switching characteristic rather than in the energy-storing memory that physically distinguishes them. Akgul et al. (2020) illustrates this pattern illustrates this pattern clearly: the memcapacitor-based oscillator is characterized using standard dynamical metrics (Lyapunov exponents, bifurcation diagrams, basins of attraction), and chaos synchronization is proposed as an engineering application, yet the analysis does not address what the σ–ϕ constitutive relation contributes beyond what a memristive nonlinearity could equally provide. No systematic study has yet characterized memcapacitor- or meminductor-based circuits against entropy or randomness standards, nor formalized the conditions under which their internal states become unobservable from external electrical measurements.

3.3 Joint operation: higher-dimensional dynamics and entropy

The most significant and least explored scenario arises when memcapacitors and meminductors operate jointly, potentially alongside a memristor. The simultaneous presence of electrical and magnetic memory introduces multiple coupled internal state variables operating across distinct energy domains: each mem-element contributes at least one independent state variable defined by its constitutive relation, producing a high-dimensional phase space whose accessible dynamics cannot be reproduced by any single mem-element type alone. This coupling prevents monotonic relaxation, increases effective state-space dimensionality, and enables hyperchaotic regimes with two or more positive Lyapunov exponents, substantially increasing the rate of information generation relative to simple chaotic circuits (Yuan and Li, 2019; Wang et al., 2023; Wang et al., 2019). Formally, such a circuit constitutes an autonomous nonlinear dynamical system dx/dt = f(x), where the state vector x ∈ ℝⁿ collects the internal memory variables of each mem-element together with the circuit’s energy- storage states, and the effective dimension n grows with the number of coupled mem-elements.

From a security standpoint, three properties of joint mem-element operation are particularly interesting. First, dimensional scaling is structural rather than incidental: each additional mem-element of a distinct type expands the accessible phase space without active components, making complexity intrinsic to the circuit topology rather than to design effort. Second, extreme multistability, i.e., the coexistence of multiple stable oscillatory regimes accessible from different initial conditions and reported in Wang et al. (2023) and Ren et al. (2024), is directly exploitable in PUF design: manufacturing variability determines which attractor the circuit settles into, producing a device-specific signature that is a function of physical fabrication rather than algorithmic choice, and whose diversity grows with attractor dimensionality. Third, and most fundamentally, inference resistance in memcapacitor–meminductor circuits has a physical rather than computational basis: because the state variables of reactive mem-elements evolve under energy-conservative dynamics, reconstructing the full system state from terminal measurements requires solving an inverse problem of substantially higher complexity than for purely resistive systems. This partial observability, analogous in structure to a hidden Markov model but defined over a continuous high-dimensional state space, provides a mechanism for inference resistance that does not depend on computational hardness assumptions, and is therefore orthogonal to classical and quantum threats.

Figures 1a,b translate these principles into two concrete MC + MI architectures: a PUF and a TRNG configuration, respectively. In both cases, the coupled nonlinear trajectory and the partial observability of the reactive mem-elements make the response hard to clone or predict. Translating joint operation into practical hardware nevertheless faces significant barriers: emulator-based MC + MI circuits require several active blocks per element, so parasitics, bandwidth, and matching limit the fidelity of the emulated dynamics, while solid-state co-integration is hindered by the incompatible material platforms on which memcapacitive and meminductive behaviors have been demonstrated (Demasius et al., 2021; Dinavahi et al., 2023; Dinavahi and Rusty Harris, 2025).

Despite this theoretical richness, existing works remain primarily phenomenological as they describe and classify the dynamical behavior of particular implementations without addressing the more fundamental questions of state observability, predictability limits, or the mapping between dynamical properties and entropy-relevant statistical descriptors. The connection between hyperchaotic dual-memory dynamics and the formal requirements of hardware-security primitives therefore remains, at present, largely unestablished. A clear boundary must be drawn between demonstrated and speculative results: chaotic, hyperchaotic, and multistable MC + MI dynamics have been verified experimentally through emulator implementations (Yuan and Li, 2019; Wang et al., 2023; Akgul et al., 2020; Wang et al., 2019; Ren et al., 2024), whereas the security-specific properties (attractor-based uniqueness, entropy quality, and inference resistance) remain theoretical propositions awaiting experimental validation.

4 Open challenges and future perspectives

Several critical questions remain unanswered and collectively define the frontier of the field. A first category concerns device availability and the limits of emulator-based validation. Circuit emulators are a scientifically valid methodology for exploring constitutive relationships and dynamical regimes (Romero et al., 2021a), but they cannot reproduce the fabrication-induced variability and noise properties that are precisely the source of security-relevant entropy in real devices. Overcoming this limitation requires dedicated characterization platforms for emerging memcapacitive implementations (ferroelectric capacitors, electrolyte-gated structures) specifically targeted at security metrics, rather than at neuromorphic or storage applications.

A second deeper challenge concerns the absence of appropriate benchmarking frameworks. No systematic theoretical framework yet characterizes the observability and predictability limits of memcapacitor–meminductor circuits from externally accessible electrical signals. Current evaluation tools such as NIST SP 800–22 and standard PUF metrics (uniqueness, reliability, uniformity) were designed for digital circuits and do not capture properties specific to continuous-state analog devices. New metrics grounded in dynamical systems theory, the Kolmogorov–Sinai entropy rate as a measure of analog entropy generation, or mutual information between terminal measurements and internal state variables as a proxy for inference resistance, are needed and have yet to be developed or validated against dual-memory circuits. Formally, the accessible terminal signals define an output map y(t) = h(x(t)), where y(t) collects the measurable voltages and currents and x(t) the full internal state; since h is generally non-injective, x(t) cannot be uniquely recovered from y(t), and the extent of this irrecoverability quantifies the intrinsic inference resistance of the circuit. By Pesin’s identity, h_KS = Σ λᵢ⁺, the sum of the positive Lyapunov exponents, directly linking entropy generation to the hyperchaotic dynamics characterized above. A practical route toward standardization is to estimate these indicators from measured time series using established embedding and Lyapunov-spectrum algorithms, validate them on emulator testbeds against a ground-truth model, and ultimately incorporate them as extensions of entropy-source validation methodologies such as NIST SP 800-90B.

A third gap concerns the formalization of resistance to modelling attacks. The expanded state-space dimensionality of reactive mem-element circuits is qualitatively argued to improve resilience against machine-learning-based adversaries, but no formal bound on the sample complexity required for successful modelling attacks has been established. Deriving such bounds, analogous to Vapnik–Chervonenkis-dimension arguments adapted to continuous nonlinear dynamical systems, would transform a qualitative intuition into a verifiable security claim.

Finally, four practical challenges will ultimately determine deployability: device-to-device variability, long-term stability, aging, and CMOS integration. Variability is double-edged, providing the entropy that sustains uniqueness while threatening response reproducibility; failure modes under cycling and thermal stress remain largely uncharacterized for memcapacitors and meminductors; and no mem-element material family is yet process-compatible with the others or with standard CMOS flows. These device-level problems are expected to intensify as system complexity grows: each added mem-element multiplies the sources of variability and drift, and in a coupled nonlinear circuit aging of a single device can reshape the attractor landscape or cross a bifurcation boundary. Reliability engineering must therefore scale with the dimensionality that provides the security benefits.

5 Discussion

The asymmetry documented in this review reflects less a judgment about relative security value than the historical accident of technological maturation: memristors achieved experimental demonstration decades before memcapacitors and meminductors, and security researchers naturally followed the available technology. The field has consequently operated within a restricted design space, compounded by the gap between the nonlinear dynamics community, which has characterized dual-memory oscillators without security motivation, and the hardware security community, which has overlooked the dynamical advantages of reactive memory elements. Bridging these perspectives is the most urgent open direction in this field.

Established approaches such as SRAM-PUFs (Holcomb et al., 2009), ring-oscillator PUFs (Suh and Devadas, 2007), and quantum random number generators (Herrero-Collantes and Garcia-Escartin, 2017) each offer well-characterized entropy sources, but none combines history dependence, energy-storing memory, and intrinsic high-dimensional chaos within a single passive circuit element. The unique advantage of memcapacitor–meminductor systems lies precisely in this confluence: complexity, partial non-observability, and device-specific variability emerge together from the same physical mechanism, without requiring digital post-processing or external noise injection. The mathematical framework to exploit this is already in place (Di Ventra et al., 2009; Radwan and Fouda, 2015), namely, the constitutive formalism of mem-elements combined with standard tools of nonlinear dynamical systems theory (state-space modelling, Lyapunov analysis, and nonlinear observability); what is missing is its systematic application to security-oriented circuit design.

From a practical standpoint, reliance on circuit emulators is a temporary but scientifically valid limitation. As occurred historically with the memristor, whose theoretical foundations preceded experimental realization by nearly 4 decades (Chua, 1971; Strukov et al., 2008), anticipatory characterization of memcapacitor and meminductor systems is not only justified but necessary. A plausible research roadmap spans three horizons: in the short term (1–3 years), circuit-theoretic analysis of observability limits and emulator-based evaluation against established randomness standards (NIST SP 800–22, AIS-31); in the medium term (3–5 years), device-level validation of emulator predictions on emerging solid-state memcapacitors (Demasius et al., 2021); and in the longer term (5+ years), the deliberate engineering of the high-dimensional state space of multi-mem-element circuits into deployable security primitives: an opportunity that is, at present, entirely unrealized.

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Footnotes

Edited by: Sungsik Lee, Pusan National University, Republic of Korea

Reviewed by: Danyoung Cha, Pukyong National University, Republic of Korea

Hyeri Kim, Pusan National University, Republic of Korea